西安石油大学机械工程学院,西安,710065
网络首发:2021-08-10,
纸质出版:2021
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苏亚丽, 赖俊桦, 钱俊杰, 等. 真空栅介质场效应晶体管自热效应模型[J]. 西安交通大学学报, 2021,55(8):85-92.
Self-Heating Effect Model for Vacuum Gate Dielectric Field-Effect Transistors[J]. 2021, 55(8): 85-92.
苏亚丽, 赖俊桦, 钱俊杰, 等. 真空栅介质场效应晶体管自热效应模型[J]. 西安交通大学学报, 2021,55(8):85-92. DOI: 10.7652/xjtuxb202108011.
Self-Heating Effect Model for Vacuum Gate Dielectric Field-Effect Transistors[J]. 2021, 55(8): 85-92. DOI: 10.7652/xjtuxb202108011.
针对纳米尺度金属氧化物半导体场效应晶体管(MOSFET)热传输尺度效应对自热效应影响加剧的问题
提出一种考虑尺度影响的真空栅介质垂直堆叠硅纳米线(SiNWs)环栅场效应晶体管(GAA FET)自热效应模型。首先
分析硅薄膜与SiNWs内声子散射自由程之间的关系
量化用于衡量声子边界散射的SiNW热导率衰减因子; 然后
根据国际上现阶段关于纳米硅薄膜热导率的解析模型
推导得到考虑尺度效应影响的SiNW热导率解析模型; 最后
结合纳尺度器件热传输的关键路径
建立起考虑尺度影响的GAA SiNWs FET自热效应模型。在TCAD软件中采用所提自热效应模型实现了GAA SiNWs FET自热效应的数值计算。仿真结果表明:低热导率真空栅介质、垂直堆叠多热源与热传输尺度效应将导致真空栅介质GAA SiNWs FET热生成与扩散过程更加复杂
加剧器件自热效应; 通过真空栅介质间隙与环绕气体压强之间的折中设计能够最大化栅极热传输能力
达到抑制器件自热效应以改善器件性能及其可靠性的目的; 与传统自热效应模型估算的热点温度值相比
所提出的自热效应模型预测的真空栅器件内热点温度提高了30%
表明该自热效应模型能够有效的揭示GAA FET内SiNW热传输尺度效应对自热效应的影响机制。
A self-heating effect model for vacuum gate dielectric vertical-stacked silicon nanowires(SiNWs)gate-all-around field-effect transistors(GAA FETs)considering scale effect is proposed to address intensified influences of thermal transport scale effect on self-heating effect in nanoscale MOSFETs. Firstly
the relationships between phonon scattering free paths in silicon film and SiNW are analyzed
and the SiNW thermal conductivity attenuation factor used to measure the revealing phonon boundary scattering is quantified. Then an analytical model of the thermal conductivity of SiNW considering the influence of scale effect is derived based on the current international analytical model for nanoscale silicon films. Finally
the self-heating effect model considering the scale effect is established for GAA SiNWs FET by combining with the critical path of heat transfer in nanoscale devices. The proposed model is used to realize numerical simulation of the self-heating effect of GAA SiNWs FET in TCAD software. Simulation results show that the vacuum gate dielectric with low thermal conductivity
vertical stacked multiple heat sources and thermal transport scale effect lead to more complex heat generation and diffusion processes in vacuum gate dielectric GAA SiNWs FET
and aggravate the self-heating effect of devices. The thermal transport capacity of gate can be maximized through the compromise design between vacuum gate gap and surrounding gas pressure and the self-heating effect of the device can be inhibited to improve the performance and reliability of device. Compared with the hot spot temperature estimated by the traditional self-heating effect model
the hot spot temperature in the vacuum gate device predicted by the proposed model increases by 30%
indicating that the proposed model can effectively reveal the thermal transport scale effect of SiNW in GAA FET.
SHRIVASTAVA M, AGRAWAL M, MAHAJAN S, et al. Physical insight toward heat transport and an improved electrothermal modeling framework for FinFET architectures [J]. IEEE Transactions on Electron Devices, 2012, 59(5): 1353-1363.
MYEONG I, SON D, KIM H, et al. Thermal-aware shallow trench isolation design optimization for minimizing IOFF in various sub-10-nm 3-D transistors [J]. IEEE Transactions on Electron Devices, 2018, 66(1): 647-654.
刘一婷, 宫兴, 闫娜. 围栅硅纳米线MOSFET器件的仿真研究 [J]. 微处理机, 2018, 39(2): 1-4.
LIU Yiting, GONG Xing, YAN Na. Simulation study on gate-all-around MOSFET [J]. Microprocessors, 2018, 39(2): 1-4.
李尊朝, 罗诚, 王闯, 等. 部分耗尽异质环栅场效应晶体管阈值电压模型 [J]. 西安交通大学学报, 2013, 47(12): 50-54.
LI Zunchao, LUO Cheng, WANG Chuang, et al. Threshold voltage modeling of partially-depleted dual-material surrounding gate field-effect transistor [J]. Journal of Xi'an Jiaotong University, 2013, 47(12): 50-54.
尤一龙, 李尊朝, 刘林林, 等. 一种围栅金属氧化物半导体场效应管阈值电压模型 [J]. 西安交通大学学报, 2010, 44(2): 77-81.
YOU Yilong, LI Zunchao, LIU Linlin, et al. A threshold voltage model for surrounding gate metal-oxide-semiconductor field-effect transistor [J]. Journal of Xi'an Jiaotong University, 2010, 44(2): 77-81.
张战刚, 雷志锋, 童腾, 等. 14 nm FinFET和65 nm平面工艺静态随机存取存储器中子单粒子翻转对比 [J]. 物理学报, 2020, 69(5): 056101.
ZHANG Zhangang, LEI Zhifeng, TONG Teng, et al. Comparison of neutron induced single event upsets in 14 nm FinFET and 65 nm planar static random access memory devices [J]. Acta Physica Sinica, 2020, 69(5): 056101.
LEE Y M, NA M H, CHU A, et al. Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology [C]∥63rd IEEE International Electron Devices Meeting. Piscataway, NJ, USA: IEEE, 2017: 29.
徐进朋, 尤一龙, 李尊朝, 等. 围栅金属氧化物半导体场效应管电流模型 [J]. 西安交通大学学报, 2010, 44(10): 57-61.
XU Jinpeng, YOU Yilong, LI Zunchao, et al. A current model for surrounding gate metal-oxide-semiconductor field-effect transistor [J]. Journal of Xi'an Jiaotong University, 2010, 44(10): 57-61.
HAN J W, AHN J H, CHOI Y K. Damage immune field effect transistors with vacuum gate dielectric [J]. Journal of Vacuum Science Technology: B, 2011, 29(1): 011014.
HAN J W, MOON D I, SUB O J, et al. Vacuum gate dielectric gate-all-around nanowire for hot carrier injection and bias temperature instability free transistor [J]. Applied Physics Letters, 2014, 104(25): 253506.
黄宁, 赵婉婉, 刘伟景, 等. 环栅纳米线FET自热效应及微尺度空间效应研究 [J]. 半导体技术, 2019(12): 7.
HUANG Ning, ZHAO Wangwang, LIU Jingwei, et al. Investigation of self-heating effect and microscale spatial effect for gate-all-around nanowire FET [J]. Semiconductor Technology, 2019(12): 7.
PARK W, SHIN D D, KIM S J, et al. Phonon conduction in silicon nanobeams [J]. Applied Physics Letters, 2017, 110(21): 213102.
PARK J Y, YUN D H, KIM S Y, et al. Suppression of self-heating effects in 3-D V-NAND flash memory using a plugged pillar-shaped heat sink [J]. IEEE Electron Device Letters, 2018, 40(2): 212-215.
CHUNG C C, LIN H H, WAN W K, et al. Thermal SPICE modeling of FinFET and BEOL considering frequency-dependent transient response, 3-D heat flow, boundary/alloy scattering, and interfacial thermal resistance [J]. IEEE Transactions on Electron Devices, 2019, 66(6): 2710-2714.
HUANG N, LIU W, LI Q, et al. Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs [J]. Microelectronics Journal, 2020, 95: 104679.
CAI L, CHEN W, DU G, et al. Layout design correlated with self-heating effect in stacked nanosheet transistors [J]. IEEE Transactions on Electron Devices, 2018, 65(6): 2647-2653.
XU C, KOLLURI S K, ENDO K, et al. Analytical thermal model for self-heating in advanced FinFET devices with implications for design and reliability [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(7): 1045-1058.
LIU W, ASHEGHI M. Phonon-boundary scattering in ultrathin single-crystal silicon layers [J]. Applied Physics Letters, 2004, 84(19): 3819-3821.
VASILESKA D, RALEVA K, GOODNICK S M. Electrothermal studies of FD SOI devices that utilize a new theoretical model for the temperature and thickness dependence of the thermal conductivity [J]. IEEE Transactions on Electron Devices, 2010, 57(3): 726-728.
MCGAUGHEY A J H, LANDRY E S, SELLAN D P, et al. Size-dependent model for thin film and nanowire thermal conductivity [J]. Applied Physics Letters, 2011, 99(13): 131904.
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