用于高速模数转换器的非对称全差分参考电压缓冲器

焦子豪 1; 张瑞智 1; 金锴 1; 盛炜 2; 张鸿 1

doi:10.7652/xjtuxb202005015

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用于高速模数转换器的非对称全差分参考电压缓冲器

更新时间：2025-07-09

- 用于高速模数转换器的非对称全差分参考电压缓冲器
- Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors
- 西安交通大学学报 2020年54卷第5期页码：109-116
- 作者机构：
  
  西安交通大学微电子学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2019-09-23。作者简介: 焦子豪(1996—),男,硕士生;张鸿(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(61974118)
- DOI：10.7652/xjtuxb202005015
  中图分类号： TN432
- 网络首发：2020-05-10，
  
  纸质出版：2020
- 稿件说明：
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焦子豪 1, 张瑞智 1, 金锴 1, 等. 用于高速模数转换器的非对称全差分参考电压缓冲器[J]. 西安交通大学学报, 2020,54(5):109-116.

Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors[J]. 2020, 54(5): 109-116.
焦子豪 1, 张瑞智 1, 金锴 1, 等. 用于高速模数转换器的非对称全差分参考电压缓冲器[J]. 西安交通大学学报, 2020,54(5):109-116. DOI： 10.7652/xjtuxb202005015.

Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors[J]. 2020, 54(5): 109-116. DOI： 10.7652/xjtuxb202005015.

摘要

针对现有高速高精度模数转换器(ADC)芯片内部参考电压缓冲器需要牺牲很大功耗来满足精度和速度要求的问题

提出了一种具有非对称AB类输出级的全差分参考电压缓冲器

能够以较低的运放增益满足缓冲器高精度的需求

从而显著降低缓冲器的功耗。通过引入非对称的输出结构

参考电压缓冲器只需要满足高带宽

不再需要较高的开环增益; 输入级采用互补结构进一步降低了功耗; 为了消除传统结构所引入的高阻节点

提出了低输出阻抗的AB类驱动电路

提高了带宽。仿真结果表明

在负载为20 pF的片内滤波电容的情况下

参考电压缓冲器的功耗为27 mW

建立时间小于2.5 ns

与相近性能的电路相比

所提电路的功耗更低。其中运放的单位增益带宽为602 MHz

相位裕度为61°。所提出的参考电压缓冲器应用于一款双通道14位200 MHz的流水线ADC中

测试结果表明

ADC的信号噪声失真比达到73 dB

所提出的电路结构能以较低的功耗实现较高的精度和速度。

Abstract

For solving the problem that the internal reference voltage buffer of high-speed analog-to-digital converter(ADC)has to consume large power to achieve high accuracy and high sampling rate

a fully differential reference voltage buffer with an asymmetric class-AB output stage is presented. The voltage buffer achieves high precision with a relatively low op-amp gain

which significantly reduces the power consumption of the buffer. By introducing an asymmetric output structure

the circuit only needs to satisfy large bandwidth but no longer needs a high open-loop gain

and the input stage uses a complementary structure to further reduce power consumption. A class-AB driving circuit with low output impedance eliminates the high-resistance nodes introduced by the common structure and increases the bandwidth. Simulation results show that the power consumption of this reference voltage buffer is 27 mW and the settling time is less than 2.5 ns when driving a 20 pF on-chip filtering capacitor

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references

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