高性能的图像无损压缩知识产权核设计

黄绪; 梁煜; 张为; 郝亚喆

doi:10.7652/xjtuxb202005014

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高性能的图像无损压缩知识产权核设计

更新时间：2025-07-09

- 高性能的图像无损压缩知识产权核设计
- Design of Intellectual Property Core for High-Performance Image Lossless Compression
- 西安交通大学学报 2020年54卷第5期页码：102-108+123
- 作者机构：
  
  天津大学微电子学院,天津,300072
- 作者简介：
- 基金信息：
  
  : 2019-11-30。作者简介: 黄绪(1995—),男,硕士生;张为(通信作者),男,教授,博士生导师。基金项目: 光电信息控制和安全技术重点实验室资助项目(JCKY2019210C053);国家重点研发计划资助项目(2016YFE0100400)
- DOI：10.7652/xjtuxb202005014
  中图分类号： 510.1035
- 网络首发：2020-05-10，
  
  纸质出版：2020
- 稿件说明：
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黄绪, 梁煜, 张为, 等. 高性能的图像无损压缩知识产权核设计[J]. 西安交通大学学报, 2020,54(5):102-108+123.

Design of Intellectual Property Core for High-Performance Image Lossless Compression[J]. 2020, 54(5): 102-108+123.
黄绪, 梁煜, 张为, 等. 高性能的图像无损压缩知识产权核设计[J]. 西安交通大学学报, 2020,54(5):102-108+123. DOI： 10.7652/xjtuxb202005014.

Design of Intellectual Property Core for High-Performance Image Lossless Compression[J]. 2020, 54(5): 102-108+123. DOI： 10.7652/xjtuxb202005014.

摘要

为了解决海量图像数据对存储介质和有限的带宽造成的巨大压力

提出了高性能的图像无损压缩知识产权(IP)核

给出了相应的超大规模集成电路(VLSI)架构。通过对图像预处理模块进行兼容性优化

使其可以灵活处理多种规格的图像; 优化离散小波变换(DWT)模块

提出了单加法器延时结构

使离散小波变换模块的最高工作频率达274 MHz; IP核整体架构采用串并复用流水线设计思路

图像预处理和离散小波变换模块串行处理数据

算术编码和位平面编码模块并行处理数据

IP核内的所有模块均采用流水线设计方法

最终大幅提升IP核的吞吐率。实验结果表明

设计的IP核可直接接收光电耦合器件(CCD)相机的图像数据完成无损压缩并输出码流

该IP核在Xilinx Kintex-7 KC705开发板上实现

最高工作频率达171 MHz

最大吞吐率达1 472 Mb/s

与现有图像无损压缩VLSI编码器相比

最高工作频率提升16%以上

最大吞吐率提升25%以上。

Abstract

To reduce the heavy burden by the massive image data on the storage medium and limited bandwidth

an intellectual property(IP)core is proposed for high-performance image lossless compression

and the corresponding VLSI circuit structure is given. The image pre-processing structure is optimi-ed for compatibility

so that it can flexibly process images of multiple specifications. The discrete wavelet transform structure is optimi-ed

and a single adder delay structure is proposed

so that the maximum working frequency of the discrete wavelet transform module is 274 MH-. The serial-parallel multiplexing pipeline design is proposed for the overall structure

and discrete wavelet transform module is used as a multiplexing module. The arithmetic coding and bit plane coding modules are used together as parallel modules

so the throughput of IP core is greatly improved. The experimental results show that the IP core of this design can directly receive the image data of the CCD camera to perfor

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references

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