用于高速模数转换器的电荷泵型低抖动时钟管理电路

李楠楠 1; 黄正波 1; 季惠才 2; 盛炜 2; 张鸿 1

doi:10.7652/xjtuxb202001020

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用于高速模数转换器的电荷泵型低抖动时钟管理电路

更新时间：2025-07-09

- 用于高速模数转换器的电荷泵型低抖动时钟管理电路
- A Low Jitter Charge Pump Based Clock Management Circuit for High Speed Analog-to-Digital Converters
- 西安交通大学学报 2020年54卷第1期页码：162-168
- 作者机构：
  
  西安交通大学微电子学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2019-07-10。作者简介: 李楠楠(1996—),男,硕士生;张鸿(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(61974118);模拟集成电路重点实验室基金资助项目(6142802180105)
- DOI：10.7652/xjtuxb202001020
  中图分类号： TN432
- 网络首发：2020-01-10，
  
  纸质出版：2020
- 稿件说明：
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李楠楠 1, 黄正波 1, 季惠才 2, 等. 用于高速模数转换器的电荷泵型低抖动时钟管理电路[J]. 西安交通大学学报, 2020,54(1):162-168.

A Low Jitter Charge Pump Based Clock Management Circuit for High Speed Analog-to-Digital Converters[J]. 2020, 54(1): 162-168.
李楠楠 1, 黄正波 1, 季惠才 2, 等. 用于高速模数转换器的电荷泵型低抖动时钟管理电路[J]. 西安交通大学学报, 2020,54(1):162-168. DOI： 10.7652/xjtuxb202001020.

A Low Jitter Charge Pump Based Clock Management Circuit for High Speed Analog-to-Digital Converters[J]. 2020, 54(1): 162-168. DOI： 10.7652/xjtuxb202001020.

摘要

针对高速模数转换器(ADC)对时钟信号的占空比以及低抖动的要求

提出了一种电荷泵型的时钟管理电路

利用电荷泵构成两个闭环回路

分别实现占空比稳定和可调双相不交叠时钟产生功能。电荷泵对时钟相位的积分功能可实现宽范围的时钟占空比调节

并能明显抑制电源噪声对时钟下降沿抖动的影响。该时钟管理电路采用0.18 μm标准CMOS工艺设计。版图寄生参数提取后的仿真结果表明:该时钟管理电路可在40～200 MHz频率范围内

将20%～80%的输入占空比稳定地调整到45%～55%的范围内; 在200 mV电源干扰的条件下

输出时钟抖动可降低到传统RC型占空比稳定电路的1/10之下。将该时钟电路应用于一款双通道、200MSPS、14位的流水线ADC中

测试结果表明ADC的信号噪声失真比达到了73.01 dB。

Abstract

To fulfil the requirements of wide-range duty cycle adjustment and low jitter for the clock signals of high-speed analog-to-digital converters(ADC)

a charge-pump type clock management circuit was proposed

which uses charge pumps to form two closed loops

achieving wide-range duty cycle stabili-ation and adjustable two-phase non-overlapping clock generation. The charge pump-s integral function of the clock phase extends the range of the input clock duty cycle stabili-ation and significantly suppresses the effect of power supply noise on the falling edge of the clock. Designed in a 0.18 -m standard CMOS process

the post-layout simulation results showed that the input signal frequency range of the proposed clock management circuit is 40-200 MH-

and the clock duty cycle can be stably adjusted into the range of 45%-55% within an input duty cycle of 20%-80%. Under the condition of 200 mV power supply interference

the output clock jitter can be reduced by a factor of ten compared with

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references

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