西安交通大学电子与信息工程学院,西安,710049
网络首发:2015-02-10,
纸质出版:2015
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张鸿, 张牡丹, 张杰, 等. 用于植入式医疗装置的逐次逼近式模数转换器[J]. 西安交通大学学报, 2015,49(2):43-48+129.
A Successive Approximation Register Analog-to-Digital Converter for Implantable Biomedical Devices[J]. 2015, 49(2): 43-48+129.
张鸿, 张牡丹, 张杰, 等. 用于植入式医疗装置的逐次逼近式模数转换器[J]. 西安交通大学学报, 2015,49(2):43-48+129. DOI: 10.7652/xjtuxb201502008.
A Successive Approximation Register Analog-to-Digital Converter for Implantable Biomedical Devices[J]. 2015, 49(2): 43-48+129. DOI: 10.7652/xjtuxb201502008.
针对植入式医疗装置对模数转换器(ADC)的超低功耗和高精度要求
提出了一种共模恒定型分段混合编码结构的逐次逼近式模数转换器(SAR-ADC)。该SAR-ADC的电容数模转换器DAC中采用分段混合编码结构
兼具了分段二进制编码的低功耗优势和分段温度计编码的高线性度优势。共模恒定型控制方式具有极低的动态功耗。采用HHNEC 0.35 μm CMOS工艺完成了10位共模恒定型分段混合编码SAR-ADC的电路和版图设计。后仿真结果表明:所设计的SAR-ADC的电源电压范围为1.8~3 V; 在采样率为10
3
s
-1
的条件下
其有效位数为9.4位; 整个SAR-ADC所消耗的电流仅为60 nA
在同等工艺条件下具有更低的功耗; 所设计的转换器能够满足心脏起搏器等植入式医疗装置的需求。
A hybrid encoded successive approximation register(SAR)analog-to-digital converter(ADC)with constant common-mode control logic is presented to meet the requirements of ultra low power consumption and high resolution for implantable biomedical devices. The hybrid encoded structure of the split capacitive digital to analog converter(CDAC)employed in the SAR-ADC combines the low-power feature of binary encoded CDAC and the high-linearity advantage of thermometer encoded CDAC. The constant common-mode control logic has the advantage of ultra low dynamic power dissipation. The schematic and layout of a 10 bit SAR ADC are designed using the HHNEC 0.35 μm CMOS technology. Simulation results after layout parasitic extraction show that the pro
posed SAR-ADC operates under a power supply range of 1.8-3 V
and achieves an effective bit of 9.4 under a sampling rate of 10
3
s
-1
. The current consumption is only 60 nA
which is lower than those recently reported SAR ADCs with similar fabrication technologies. It can be concluded that the proposed converter is suitable for implantable devices such as cardiac pace makers.
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