一种新型高阶两通道时间交织ΣΔ调制器系统结构

杨骁; 陈贵灿; 程军; 徐晓云

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一种新型高阶两通道时间交织ΣΔ调制器系统结构

专题研究 | 更新时间：2025-12-08

- 一种新型高阶两通道时间交织ΣΔ调制器系统结构
- A Novel Architecture of High-Order Two-Channel Time-Interleaved ΣΔ Modulator
- 西安交通大学学报 2008年42卷第8期页码：996-1000
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2007-12-07. 作者简介: 杨骁(1978-), 男, 博士生;陈贵灿(联系人), 男, 教授, 博士生导师. 基金项目: 西安应用材料创新基金资助项目(XA-AM-200506)
- DOI：
  中图分类号： TN432
- 网络首发：2008-08-10，
  
  纸质出版：2008
- 稿件说明：
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杨骁, 陈贵灿, 程军, 等. 一种新型高阶两通道时间交织ΣΔ调制器系统结构[J]. 西安交通大学学报, 2008,42(8):996-1000.

杨骁, 陈贵灿, 程军, et al. A Novel Architecture of High-Order Two-Channel Time-Interleaved ΣΔ Modulator[J]. 2008, 42(8): 996-1000.
杨骁, 陈贵灿, 程军, 等. 一种新型高阶两通道时间交织ΣΔ调制器系统结构[J]. 西安交通大学学报, 2008,42(8):996-1000. DOI：

杨骁, 陈贵灿, 程军, et al. A Novel Architecture of High-Order Two-Channel Time-Interleaved ΣΔ Modulator[J]. 2008, 42(8): 996-1000. DOI：

摘要

为了减小两通道时间交织ΣΔ调制器中通道之间系数失配引起的折叠噪声

提出了一种新型的高阶两通道时间交织ΣΔ调制器的系统结构.通过在传统噪声传递函数(NTF)中增加一个奈奎斯特频率处的零点

得到了一种新的NTF.新增的零点减小了NTF在高频处的幅值

从而能够减小两通道时间交织调制器结构中由于系数失配引起的折叠噪声.以实现新NTF的单通道单环4阶3 位前馈分布型ΣΔ调制器结构为原型

利用多抽样率系统和块数字滤波器基本原理

得到其对应的两通道时间交织系统结构.在两个通道的系数存在1%的失配条件下

调制器的信号噪声失真比只降低了3.1 dB

这表明系数失配对该调制器的性能影响很小.

Abstract

To alleviate the folded noise due to coefficient mismatches between the two channels in two-channel time-interleaved(TI)ΣΔ modulators

a novel architecture of high-order two-channel time-interleaved ΣΔ modulator is proposed. By adding a zero to the Nyquist frequency in the conventional noise transfer function(NTF)

a new type of NTF is obtained. The amount of the folded noise can be reduced because the amplitude of the new NTF at high frequencies is reduced by the added zero. A single-channel single-loop fourth-order 3-bit distributed feedforward ΣΔ modulator is proposed to implement the new NTF. The architecture of the two-channel TI ΣΔ modulator is derived from the single-channel modulator based on the theory of multirate system and block digital filter. The degradation of the signal-to-noise-plus-distortion ratio of the proposed modulator is only 3.1 dB with 1% coefficient mismatches

which shows that the proposed architecture is insensitive to coefficient mismatches.

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Keywords

references

BALMELLI P, HUANG Q. A 25 MS/s 14-b 200-mW sigma delta modulator in 0.18 μm CMOS [J]. IEEE J Solid-State Circuits, 2004, 39(12):2161-2169.

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