一种新型级联ΣΔ调制器系统结构

杨骁; 陈贵灿; 程军; 徐晓云

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一种新型级联ΣΔ调制器系统结构

更新时间：2025-12-08

- 一种新型级联ΣΔ调制器系统结构
- A Novel Cascade ΣΔ Modulator Architecture
- 西安交通大学学报 2008年42卷第12期页码：1541-1545
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2008-04-18. 作者简介: 杨骁(1978-),男,博士生;陈贵灿(联系人), 男, 教授, 博士生导师. 基金项目: 西安应用材料创新基金资助项目(XA-AM-200506)
- DOI：
  中图分类号： TN43
- 网络首发：2008-12-10，
  
  纸质出版：2008
- 稿件说明：
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杨骁, 陈贵灿, 程军, 等. 一种新型级联ΣΔ调制器系统结构[J]. 西安交通大学学报, 2008,42(12):1541-1545.

杨骁, 陈贵灿, 程军, et al. A Novel Cascade ΣΔ Modulator Architecture[J]. 2008, 42(12): 1541-1545.
杨骁, 陈贵灿, 程军, 等. 一种新型级联ΣΔ调制器系统结构[J]. 西安交通大学学报, 2008,42(12):1541-1545. DOI：

杨骁, 陈贵灿, 程军, et al. A Novel Cascade ΣΔ Modulator Architecture[J]. 2008, 42(12): 1541-1545. DOI：

摘要

针对传统高阶级联ΣΔ调制器结构电路复杂和对运算放大器的增益和线性度要求较高的缺点

提出了一种新型的2-3两级5阶多位量化器级联ΣΔ调制器系统结构.该结构的第1级采用2阶多位量化器的低失真ΣΔ调制器结构

减小了运算放大器的非线性有限增益对调制器性能的影响.第2级采用信号传递函数等于单位增益的单环3阶ΣΔ调制器

而不是传统级联结构中1阶或2阶ΣΔ调制器

降低了电路的复杂程度.系统仿真结果表明:在最大增益为70 dB的非线性运算放大器增益、±0.2%的随机数模转换误差的非理想条件下

该调制器的最大信号噪声失真比能够达到95 dB.

Abstract

In order to overcome the disadvantages that the conventional cascade ΣΔ modulator architecture is sensitive to the nonlinear finite operational amplifier(OPAMP)gain and that its circuit is complex

a novel 2-3 two stages fifth-order multi-bit cascade ΣΔ modulator architecture is proposed. The first stage of the proposed ΣΔ modulator architecture employs a second-order multi-bit low-distortion ΣΔ modulator that can reduce the effects of the nonlinear finite OPAMP gain. The second stage employs a single-loop third-order ΣΔ modulator with a unity-gain signal transfer function instead of the conventional first-order or second-order modulators that can reduce the complexity of the circuit. Simulation results show that the signal-to-noise-plus-distortion ratio of the modulator can achieve 95 dB with a maximum gain of 70 dB for the nonlinear OPAMP and a random error of ±0.2% for the digital-to-analog converter.

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references

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BAJDECHI O, GIELEN G E, HUIJSING J H. Systematic design exploration of Delta-Sigma ADCs [J]. IEEE Trans Circuits and Syst:I, 2004, 51(1):86-95.

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BAIRD R T, FIEZ T S. Linearity enhancement of multibit sigma-delta A/D and D/A converters using data weighted averaging [J]. IEEE Trans Circuits and Syst:II, 1995, 42(12):753-762.

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