西安交通大学电子与信息工程学院,西安,710049
网络首发:2010-02-10,
纸质出版:2010
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尤一龙, 李尊朝, 刘林林, 等. 一种围栅金属氧化物半导体场效应管阈值电压模型[J]. 西安交通大学学报, 2010,44(2):77-81.
A Threshold Voltage Model for Surrounding Gate Metal-Oxide-Semiconductor Field-Effect Transistor[J]. 2010, 44(2): 77-81.
针对深亚微米金属氧化物半导体场效应管(MOSFET)多晶硅耗尽效应加剧问题
提出了一种全耗尽圆柱形围栅MOSFET阈值电压解析模型.通过求解多晶硅耗尽层电势泊松方程
得到多晶硅耗尽层上的压降
用以修正沟道区的通用边界条件.然后利用叠加原理求解沟道二维电势泊松方程
建立了圆柱形围栅MOSFET的表面势和阈值电压解析模型
并利用器件数值仿真软件Sentaurus对解析模型进行了验证.研究结果表明
衬底掺杂原子浓度越高
或多晶硅掺杂原子浓度越低
多晶硅耗尽层上的压降就越大
阈值电压偏移也越显著.与现有模型相比
该解析模型的精确度提高了34%以上.
An analytical model of threshold voltage for the full depletion cylindrical gate metal-oxide-semiconductor field-effect transistor(MOSFET)
is proposed to address the issue that polysilicon depletion effect is aggravated for deep submicron MOSFET. The potential Poisson's equation in the polysilicon depletion layer is solved to get the voltage drop in the polysilicon depletion layer
and the voltage drop is then used to modify the universal boundary conditions of the channel region. Then the 2D potential Poisson's equation in the channel is solved by using the superposition principle to construct the analytical models of surface potential and threshold voltage for the cylindrical gate MOSFET.These models are verified by device simulation software Sentaurus. The results show that the voltage drop in the polysilicon depletion layer would be larger and the corresponding threshold voltage shift would be more significant when the doping density of substrate is higher and the doping density of polysilicon is lower. Comparisons with existing models show that the precision of the derived analytical model is improved by more than 34%.
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YU Bo, SONG Jooyoung, YUAN Yu, et al. A unified analytic drain-current model for multiple-gate MOSFETs [J]. IEEE Transactions on Electron Devices, 2008, 55(8):2157-2163.
BORLI H, KOLBERG S, FJELDLY T A, et al. Precise modeling framework for short-channel double-gate and gate-all-around MOSFETs [J]. IEEE Transactions on Electron Devices, 2008, 55(10):2678-2686.
AOUAJ A, BOUZIANE A, NOUACRY A. Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET [J].International Journal of Electronics, 2005, 92(8):437-443.
KRANTI A, HALDAR R S, GUPTA R S. Optimization for improved short channel performance of surrounding/cylindrical gate MOSFET [J]. Electronics Letters, 2001, 37(8):533-534.
CHIANG T K. A new two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate(SG)MOSFET [J].Microelectronics Reliability, 2007, 47(2/3):379-383.
CHOI C H, CHIDAMBARAM P R, KHAMANKAR R, et al. Dopant profile and gate geometric effects on polysilicon gate depletion in scaled MOS [J]. IEEE Transactions on Electron Devices, 2002, 49(7):1227-1231.
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SALLESE J M, BUCHER M, LALLEMENT C. Improved analytical modeling of polysilicon depletion in MOSFET for circuit simulation [J]. Solid State Electronics, 2000, 44(6):905-912.
CHOI C H, CHIDAMBARAM P R, KHAMANKAR R, et al. Gate length dependent polysilicon depletion effects [J]. IEEE Electron Device Letters, 2002, 23(4):224-226.
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具有量子修正功能的三维蒙特卡罗MOS器件模拟.2006,40(2):183-186.
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