西安电子科技大学微电子学院,西安,710071
网络首发:2012-06-10,
纸质出版:2012
移动端阅览
戴力, 庄奕琪, 景鑫, 等. 一种新型高性能CMOS电流模式的动态规划电路[J]. 西安交通大学学报, 2012,46(6):29-35.
A Novel Dynamic Programming Circuit with High-Performance CMOS Current-Mode[J]. 2012, 46(6): 29-35.
为了提高片上网络中最优化计算的动态规划电路的速度和精确度
提出了一种CMOS电流模式的winner-take-all/loser-take-all(WTA/LTA)电路.该电路设计了一个可再生结构放大输入电流的差距并加速比较
从而提高了电流比较的解析度和速度; 使用了输出选择的方式来减小电流镜引起的失配误差
从而改善了输出电流的精确度.采用TSMC 180 nm工艺技术和1.3 V工作电压的仿真实验表明
所提出的WTA/LTA电路可以达到1 nA的解析度和99.5%的精确度
同时具有高速、低功耗特性.使用该电路作为基本计算单元的八节点动态规划电路
在相同仿真条件下与未改进的动态规划电路相比
计算延迟减小约60%
同时精确度提高约80%.
A current-mode winner-take-all/loser-take-all(WTA/LTA)circuit is presented to improve the calculation speed and precision of dynamic programming(DP)circuit for optimization in network-on-chip. A regenerative circuit is designed to amplify the difference of input currents and to accelerate the comparison
and hence the resolution and speed for current comparison is improved. The output current of the proposed WTA/LTA circuit is selected to reduce the propagation error caused by mismatch
and to improve the precision of output. Simulation results with TSMC 180 nm technology and 1.3 V power supply show that the proposed WTA/LTA design provides a resolution of 1 nA and a precision of 99.5% with high speed and low power. Comparisons between an 8-node dynamic programming circuit that uses the proposed circuit as a basic computational unit and an unimproved DP circuit under the same simulation condition show that the computation delay of the former is reduced about 60%
and precision is improved about 80%.
MAK T, LAM K P, NG H S, et al. A current-mode analog circuit for reinforcement learning problems [C]∥International Symposium on Circuits and Systems. Piscataway, NJ, USA: IEEE, 2007:1301-1304.
MAK T, LAM K P, NG H S, et al. A CMOS current-mode dynamic programming circuit [J]. IEEE Transactions on Circuits and Systems: Ⅰ, 2010, 57(12): 3112-3123.
MAK T, CHEUNG P, LUK W, et al, A DP-network for optimal dynamic routing in network-on-chip [C]∥Proceedings of IEEE/ACM International Conference on Hardware/Software Co-design and System Synthesis. New York, USA: ACM, 2009:119-128.
FISH A, MILRUD V, YADID-PECHT O. High-speed and high-precision current winner-take-all circuit [J]. IEEE Transaction on Circuits and Systems: Ⅱ, 2005, 52(3): 131-135.
FANG Yuguang, COHEN M A, KINCAID T G. Dynamic analysis of a general class of winner-take-all competitive neural networks [J]. IEEE Transaction on Neural Networks, 2010, 21(5):771-783.
PADASH M, MASHOUFI B, TAJI A, et al. A very-high resolution VLSI loser-take-all(LTA)circuit for neural networks and fuzzy systems [C]∥International Conference on Electronic Devices, Systems and Applications. Piscataway, NJ, USA: IEEE, 2011:225-228.
DEMOSTHENOUS A, SMEDLEY S, TAYLOR J. A CMOS analog winner-takes-all network for large-scale applications [J]. IEEE Transactions on Circuits and Systems:Ⅰ Fundamental Theory and Applications, 1998, 45(3): 300-304.
YU Chiencheng, TANG Yunching, LIU Binda. Design of high performance CMOS current-mode winner-take-all circuit [C]∥Proceedings of the International Conference on ASIC. Piscataway, NJ, USA: IEEE, 2003: 568-572.
TOMATSOPOULOS B, DEMOSTHENOUS A. Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits [C]∥Proceedings of European Conference on Circuit Theory and Design. Piscataway, NJ, USA: IEEE, 2005: 241-244.
DLUGOSZ R, TALASKA T. Low power current-mode binary-tree asynchronous Min-Max circuit [J]. Microelectronics Journal, Elsevier, 2010, 41(1):64-73.
牛秀卿, 陈宇. 新型CMOS电流比较器设计[J].南开大学学报:自然科学版, 2001, 34(2): 88-90.
NIU Xiuqin, CHEN Yu. A novel type of CMOS current comparator [J]. Acta Scientiarum Naturalium Universitatis Nakaiensis, 2001, 34(2):88-90.
陈卢,石秉学,卢纯. 一种新型的高性能CMOS电流比较器电路[J].半导体学报,2001,22(3):362-365.
CHEN Lu, SHI Bingxue, LU Chun. A novel high-performance CMOS current comparator [J]. Chinese Journal of Semiconductors, 2001, 22(3): 362-365.
BANKS D, TOUMAZOU C. Low-power high-speed current comparator designs [J]. Electronics Letters, 2008, 44(3): 171-172.
孙泳,来逢昌. 一种高电源效率开关电流比较器[J]. 固体电子学研究与进展, 2009,29(4):579-583.
SUN Yong, LAI Fengchang. A high power efficient switched current comparator [J]. Research Progress of Solid State Electronics, 2009, 29(4):579-583.
王小力,刘云涛. 12位100 MHz Bicmos流水线模数转换器的设计. 2008,42(10):1204-1208.
戚建烨,王小力,王守军. 移动数字电视调谐器中低噪声模拟滤波器的设计. 2009,43(2):72-76.
葛晨阳,郑南宁,任鹏举,等. 平板电视数字视频后处理芯片的设计与实现. 2008,42(10):1285-1289.
贾华宇,陈贵灿,程军,等. 流水线模数转换器的一种数字校准技术. 2008,42(8):991-995.
张鸿,陈贵灿,程军,等. 流水线模数转换器中高速低功耗开环余量放大器的设计. 2008,42(6):751-755.
李清华,邵志标,耿莉. 面电感设计与建模. 2007,41(4):463-466.
刘金华,陈贵灿,张鸿. 采用冲激敏感函数的差分LC振荡器相位噪声分析. 2010,44(12):66-70.
马晓龙,陈贵灿. 固定位宽乘法器的量化误差补偿方法及电路实现. 2011,45(12):75-81.
刘晔,张璐,杨新伟,等. 采用硬件神经电路的压力传感器零点温漂补偿研究. 2010,44(8):10-14.
王润新,刘进军,侯丹. 用于实现互联系统仿真的电源模块大信号模型. 2009,43(6):76-81.
杨骁,陈贵灿,程军,等. 一种新型级敛Δ调制器系统结构. 2008,42(12):1541-1545.
杨骁,陈贵灿,程军,等. 一种新型高阶两通道时间交织ΣΔ调制器系统结构. 2008,42(8):996-1000.
胡晓菁,宋政湘,王建华,等. 运用电路蕴涵及拓扑信息提高数字电路故障压缩效率. 2008,42(8):958-962.
路宏敏,安晋元,赵益民,等. 印制线拐角的频域分析. 2007,41(12):1451-1454.
翟小社,王建华,宋政湘,等. 信号完整性分析中时域宏模型结合电路仿真的方法研究. 2007,41(6):631-635.
潘金艳,朱长纯,刘永相,等. 丝网印刷碳纳米管显示器驱动电路的研制. 2007,41(10):1197-1201.
李清华,邵志标,耿莉. 一种多层平面电感设计的全局优化方法. 2007,41(6):665-668.
0
浏览量
4
下载量
1
CSCD
关联资源
相关文章
相关作者
相关机构
京公网安备11010802024621