嵌入式电容层析成像系统的成像加速方法研究

陆程程; 胡红利; 唐凯豪; 单宇杰; 黄敬轩; 董海健

doi:10.7652/xjtuxb202403017

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嵌入式电容层析成像系统的成像加速方法研究

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- 嵌入式电容层析成像系统的成像加速方法研究
- Research on an Imaging Acceleration Method for Embedded Systems of Electrical Capacitance Tomography
- 西安交通大学学报 2024年58卷第3期页码：183-192
- 作者机构：
  
  1. 西安交通大学电力设备电气绝缘国家重点实验室,西安,710049
  2. 四川大学电气工程学院,成都,610065
  3. 西安西电电力电容器有限责任公司,西安,710082
- 作者简介：
  
  : 2023-06-20。作者简介: 陆程程(2000—),女,硕士生
  胡红利(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(52177009)
- 基金信息：
  
  : 2023-06-20。作者简介: 陆程程(2000—),女,硕士生;胡红利(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(52177009);四川省自然科学基金资助项目(2023NSFSC1426);四川大学中央高校基本科研业务费项目(2023SCU12007)。
- DOI：10.7652/xjtuxb202403017
  中图分类号： TN911.7
- 网络首发：2024-03-10，
  
  纸质出版：2024
- 稿件说明：
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陆程程, 胡红利, 唐凯豪, 等. 嵌入式电容层析成像系统的成像加速方法研究[J]. 西安交通大学学报, 2024,58(3):183-192.

LU Chengcheng, HU Hongli, TANG Kaihao, et al. Research on an Imaging Acceleration Method for Embedded Systems of Electrical Capacitance Tomography[J]. 2024, 58(3): 183-192.
陆程程, 胡红利, 唐凯豪, 等. 嵌入式电容层析成像系统的成像加速方法研究[J]. 西安交通大学学报, 2024,58(3):183-192. DOI： 10.7652/xjtuxb202403017.

LU Chengcheng, HU Hongli, TANG Kaihao, et al. Research on an Imaging Acceleration Method for Embedded Systems of Electrical Capacitance Tomography[J]. 2024, 58(3): 183-192. DOI： 10.7652/xjtuxb202403017.

摘要

为了提高嵌入式系统设计中电容层析成像(ECT)的图像重构速度

研究了一种针对进阶精简指令集机器加上现场可编程门阵列(ARM+FPGA)硬件架构的图像重构算法加速技术。针对广泛应用且鲁棒的Landweber迭代算法(ILA)

首先分析算法结构

然后基于FPGA的流水线特点

改进ILA涉及的循环结构

从而达到加速的效果。同时

针对ARM+FPGA架构的特点

讨论了ARM核与FPGA核各自的任务分配方式

进一步优化了算法速度。为了验证算法的有效性

分别在使用MATLAB编程和使用提出的加速方法搭建的ZYNQ平台进行了图像重构实验

从图像重构耗时、图像相对误差和图像相关系数3个指标论证提出方法的有效性。实验结果显示

使用搭建的ZYNQ平台进行Landweber算法成像时

每个图像的运行时间比使用MATLAB编程的运行时间减少了30%～40%。该研究在保持重构精度的同时有效提升了迭代算法的速度

对于ECT系统的硬件加速具有一定适用性。

Abstract

To increase the image reconstruction speed of electrical capacitance tomography(ECT)in embedded system design

this paper proposes an acceleration method for image reconstruction algorithm in the context of the ARM+FPGA hardware architecture. The structure of the widely-used and robust iterative Landweber algorithm(ILA)is analyzed and then the loop structure within the ILA is modified taking advantage of the FPGA's pipeline features to achieve acceleration. Furthermore

according to the characteristics of the ARM+FPGA architecture

the task allocation of ARM and FPGA cores is discussed to further optimize the speed of the algorithm. To validate the effectiveness of the proposed algorithm

image reconstruction experiments are conducted on both a desktop computer(using MATLAB programming)and the ZYNQ platform(using the acceleration method proposed in this paper). The effectiveness of the proposed method is demonstrated using three parameters: image reconstruction time

relative error of the reconstructed image

and image correlation coefficient. The experimental results show that when using the platform built in this paper for imaging with ILA

the runtime for each image is reduced by 30%—40% compared with the time when using MATLAB programming on a PC. This study effectively increases the speed of iterative algorithm while maintaining reconstruction accuracy

demonstrating its applicability to hardware acceleration of ECT systems.

关键词

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references

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