统一计算架构下的装配精度并行计算模型

苏裕林; 刘浩; 苏琦; 贾康; 洪军

doi:10.7652/xjtuxb202306012

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统一计算架构下的装配精度并行计算模型

—————————————————————— | 更新时间：2025-05-08

- 统一计算架构下的装配精度并行计算模型
- Parallel Computing Model for Assembly Accuracy with Compute Unified Device Architecture
- 西安交通大学学报 2023年57卷第6期页码：105-114
- 作者机构：
  
  1. 西安交通大学现代设计与轴承转子教育部重点实验室,西安,710049
  2. 西安交通大学软件学院,西安,710049
  3. 西安交通大学机械工程学院,西安,710049
- 作者简介：
  
  : 2022-11-03。作者简介: 苏裕林(1995—),男,硕士生
  贾康(通信作者),男,副研究员,硕士生导师。基金项目: 国家自然科学基金资助项目(52075427)。
- 基金信息：
  
  : 2022-11-03。作者简介: 苏裕林(1995—),男,硕士生;贾康(通信作者),男,副研究员,硕士生导师。基金项目: 国家自然科学基金资助项目(52075427)。
- DOI：10.7652/xjtuxb202306012
  中图分类号： TH164
- 网络首发：2023-06-10，
  
  纸质出版：2023
- 稿件说明：
移动端阅览
苏裕林, 刘浩, 苏琦, 等. 统一计算架构下的装配精度并行计算模型[J]. 西安交通大学学报, 2023,57(6):105-114.

SU Yulin, LIU Hao, SU Qi, et al. Parallel Computing Model for Assembly Accuracy with Compute Unified Device Architecture[J]. 2023, 57(6): 105-114.
苏裕林, 刘浩, 苏琦, 等. 统一计算架构下的装配精度并行计算模型[J]. 西安交通大学学报, 2023,57(6):105-114. DOI： 10.7652/xjtuxb202306012.

SU Yulin, LIU Hao, SU Qi, et al. Parallel Computing Model for Assembly Accuracy with Compute Unified Device Architecture[J]. 2023, 57(6): 105-114. DOI： 10.7652/xjtuxb202306012.

摘要

针对复杂装配体在多指标需求下装配精度计算效率低下的问题

提出了一种基于统一计算架构(CUDA)的多误差传递路径装配精度并行计算模型。首先

对局部并联结构进行旋量转换

得到涵盖串并联的小位移旋量(SDT)模型

在此基础上将装配特征作为误差传递单元

通过构建姿态变换和误差传递模型

分解误差传递过程

为后续并行计算提供支持; 然后

对多功能需求(FR)误差传递路径按类型特征进行路径合并和误差旋量复用

减少计算量和数据生成量; 最后

设计算法数据结构

根据任务需求分配线程任务、合理分配内存及降低访存时延。采用该模型对某型航发高压压气机转子的装配精度进行仿真计算

结果表明:与传统CPU模型相比

所提模型的装配精度计算速度提高了约97.3倍

能够为复杂装配体的装配精度计算和公差设计提供支持。

Abstract

Aiming at the low computing efficiency of assembly accuracy for complex assemblies under multi-index requirements

a parallel computing model for assembly accuracy with multiple error transmission paths based on the compute unified device architecture(CUDA)was proposed. Firstly

the torsor transformation was performed on the local parallel structure to obtain the SDT model covering the series and parallel structures. On this basis

the assembly feature was used as the error transfer unit to build the position transformation and error transfer model

decompose the error transfer process

and provide support for the subsequent parallel computing. Next

based on the type characteristics of the error transfer path of the multiple functional requirements(FRs)

the path was combined and the error torsor was reused to reduce the amount of computation and data generation. Finally

the algorithm data structure was designed to allocate thread tasks according to task requirements

reasonably allocate memory and reduce memory access delay. The model was used to simulate the assembly accuracy of the high pressure compressor rotor of an aeroengine

and the simulation results showed that the proposed model could compute the assembly accuracy about 97.3 times faster than a conventional CPU model and can provide support for the assembly accuracy computation and tolerance design of complex assemblies.

关键词

Keywords

references

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