用于图像识别的高能效脉冲神经网络加速器设计

张剑; 刘佳; 万贤杰; 俞宙; 韩传余; 张国和

doi:10.7652/xjtuxb202301020

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用于图像识别的高能效脉冲神经网络加速器设计

—————————————————————— | 更新时间：2025-07-09

- 用于图像识别的高能效脉冲神经网络加速器设计
- Design of High Energy Efficient Spiking Neural Network Accelerator for Image Recognition
- 西安交通大学学报 2023年57卷第1期页码：211-220
- 作者机构：
  
  1. 西安交通大学电子与信息学部,西安,710049
  2. 中国电子科技集团第二十四研究所,重庆,400060
- 作者简介：
  
  : 2022-07-29。作者简介: 张剑(1989—),男,博士生
  张国和(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(62174130)
- 基金信息：
  
  : 2022-07-29。作者简介: 张剑(1989—),男,博士生;张国和(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(62174130);国防基础加强项目(2019-JCJQ-JJ-566)。
- DOI：10.7652/xjtuxb202301020
  中图分类号： TM301
- 网络首发：2023-01-10，
  
  纸质出版：2023
- 稿件说明：
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张剑, 刘佳, 万贤杰, 等. 用于图像识别的高能效脉冲神经网络加速器设计[J]. 西安交通大学学报, 2023,57(1):211-220.

ZHANG Jian, LIU Jia, WAN Xianjie, et al. Design of High Energy Efficient Spiking Neural Network Accelerator for Image Recognition[J]. 2023, 57(1): 211-220.
张剑, 刘佳, 万贤杰, 等. 用于图像识别的高能效脉冲神经网络加速器设计[J]. 西安交通大学学报, 2023,57(1):211-220. DOI： 10.7652/xjtuxb202301020.

ZHANG Jian, LIU Jia, WAN Xianjie, et al. Design of High Energy Efficient Spiking Neural Network Accelerator for Image Recognition[J]. 2023, 57(1): 211-220. DOI： 10.7652/xjtuxb202301020.

摘要

针对基于通用处理器解决方案在图像识别应用中速度慢、功耗高的问题

提出了一种高能效的脉冲神经网络加速器设计方案。首先

采用神经形态学计算中的高并行设计思想

设计了多核并行结构来实现硬件加速; 然后

根据脉冲数据传输稀疏性的特点

采用基于事件驱动的数据传输与处理方式

设计了一对一的核间传输机制

减小了用于通信的硬件资源并提高了数据传输效率; 其次

提出了按行的数据存放方式来加快膜电压数据在存储器的存取效率; 最后

设计了结合查找表与异或的电路结构

可以快速的将事件向量转变为地址事件表达(AER)格式。采用所提加速器设计方案在现场可编程逻辑门阵列(FPGA)开发板上进行优化和部署。实验结果表明:当时钟频率采用100 MHz时

识别单张手写数字图像所需能量为1.04 mJ

仅为2.2 GHz通用中央处理器(CPU)上的串行软件程序的1/1 453.8。该加速器设计方案适用于实时性要求高和能量受限的实际场景。

Abstract

A high energy efficiency spiking neural network(SNN)accelerator is proposed to solve the problems of low-speed and high-power consumption in image recognition application based on the general processor. Firstly

a multi-core parallel structure is designed for hardware acceleration by adopting the concept of high parallel design in neuromorphic computation. Secondly

considering the sparsity of spike data transmission

the one-to-one inter-core transmission mechanism is designed based on event-driven data transmission and processing

which reduces the hardware resources used for communication and improves the data transmission efficiency. Thirdly

a data arrangement scheme is proposed to speed up the access efficiency of membrane in memory. Finally

a circuit structure combining lookups and XOR is designed

which can quickly transform the event vectors into address-event-represent(AER)format. The proposed design is optimized and implemented on the field programmable logic gate array(FPGA)development board. The experimental results show that when the clock frequency is 100 MHz

the energy required to recognize a handwritten digital image is 1.04 mJ

which is only 1/1 453.8 of the serial software program on the 2.2 GHz universal central processing unit(CPU). The proposed accelerator design scheme is suitable for the real scenarios with high real-time requirements and limited energy.

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Keywords

references

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