高吞吐率的高效视频编码熵编码并行硬件架构设计

周小朋; 梁峰; 李冰

doi:10.7652/xjtuxb202007021

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高吞吐率的高效视频编码熵编码并行硬件架构设计

更新时间：2025-07-09

- 高吞吐率的高效视频编码熵编码并行硬件架构设计
- A High-Throughput Parallel Very-Large-Scale Integration Architecture of Entropy Coding in High Efficiency Video Coding
- 西安交通大学学报 2020年54卷第7期页码：180-186
- 作者机构：
  
  西安交通大学微电子学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2020-01-27。作者简介: 周小朋(1992—),男,硕士生;梁峰(通信作者),男,副教授。基金项目: 国家自然科学基金资助项目(61474093);陕西省自然科学基金资助项目(2020SM-006)
- DOI：10.7652/xjtuxb202007021
  中图分类号： TP302
- 网络首发：2020-07-10，
  
  纸质出版：2020
- 稿件说明：
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周小朋, 梁峰, 李冰. 高吞吐率的高效视频编码熵编码并行硬件架构设计[J]. 西安交通大学学报, 2020,54(7):180-186.

A High-Throughput Parallel Very-Large-Scale Integration Architecture of Entropy Coding in High Efficiency Video Coding[J]. 2020, 54(7): 180-186.
周小朋, 梁峰, 李冰. 高吞吐率的高效视频编码熵编码并行硬件架构设计[J]. 西安交通大学学报, 2020,54(7):180-186. DOI： 10.7652/xjtuxb202007021.

A High-Throughput Parallel Very-Large-Scale Integration Architecture of Entropy Coding in High Efficiency Video Coding[J]. 2020, 54(7): 180-186. DOI： 10.7652/xjtuxb202007021.

摘要

针对超高清视频编码的实时性需求以及高效视频编码熵编码系统中存在的数据吞吐率瓶颈

提出了一种基于波前并行处理(WPP)技术的硬件架构

在提高编码并行度的同时保留了行与行的依赖性

提升了编码系统的数据吞吐率与压缩效率。该架构可以进行三线程编码树单元同步编码

提高了近3倍的编码并行性; 采用同步更新单元保证线程之间概率模型的同步更新; 单线程内的概率模型支持多个二元的符号的并行更新; 初始化单元支持对多种模式下编码单元的概率初始化; 支持在线模式和离线模式

可以更好地平衡熵编码与其他模块的吞吐差异。本设计实现的熵编码器单周期处理的平均数据量为5 b

在SMIC 55 nm工艺下

其综合频率达到300 MHz

吞吐率为1 512 Mb/s

与参考设计相比

数据吞吐率提升了89%。本设计提出的熵编码器性能满足超高清视频的实时编码需求。

Abstract

Due to the real-time requirements of ultra-high-definition video encoding and the data throughput bottleneck in the entropy encoding system

a hardware architecture based on wavefront parallel processing(WPP)technology is proposed

which improves the parallelism of coding while retaining row-to-row dependency

and provides higher throughput and compression efficiency. This architecture allows three-threaded coding tree units to be encoded simultaneously

thus improves the parallelism by nearly three times. The synchronous update unit ensures the probability models between threads can be updated simultaneously. The probability models in a single thread support parallel updating of multiple binary symbols. Initiali-ation unit can initiali-e the coding units in multiple modes. Online mode and offline mode are both supported

which can balance the throughput between entropy encoder and other modules. This entropy encoder delivers an average of 5 b per cycle. The design is synthesi-ed in SM

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references

朱秀昌, 刘峰. H. 265/HEVC视频编码新标准及其扩展 [M]. 北京: 电子工业出版社, 2016: 151-176.

ISO/IEC. High efficiency video coding, ITU-T Recommendation H. 265: ISO/IEC 23008-2 [S]. Geneva, Switzerland: ISO, 2013.

ZHOU Dajiang, ZHOU Jinjia, WEI Fei, et al. Ultra-high-throughput VLSI architecture of H. 265/HEVC CABAC encoder for UHDTV applications [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2015, 25(3): 497-507.

SZE V, CHANDRAKASAN A P, BUDAGAVI M, et al. Parallel CABAC for low power video coding [C]∥Proceedings of the 15th IEEE International Conference on Image Processing. Piscataway, NJ, USA: IEEE, 2008: 2096-2099.

TSAI C H, TANG C S, CHEN L G. A flexible fully hardwired CABAC encoder for UHDTV H. 264/AVC high profile video [J]. IEEE Transactions on Consumer Electronics, 2012, 58(4): 1329-1337.

陈成. HEVC熵编码器的VLSI架构设计 [D]. 合肥: 中国科学技术大学, 2017: 37-56.

郭勇, 王桂海, 范益波, 等. 基于HEVC标准的全高清CABAC编码器设计 [J]. 电视技术, 2014, 38(9): 71-74.

GUO Yong, WANG Guihai, FAN Yibo, et al. High definition CABAC encoder design based on HEVC [J]. Video Engineering, 2014, 38(9): 71-74.

RAMOS F L L, GOEBEL J, ZATT B, et al. Low-power hardware design for the HEVC binary arithmetic encoder targeting 8K videos [C]∥Proceedings of the 2016 29th Symposium on Integrated Circuits and Systems Design. Piscataway, NJ, USA: IEEE, 2016: 1-6.

DING L F, CHEN W Y, TSUNG P K, et al. A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications [C]∥Proceedings of the Solid-State Circuits Conference: Digest of Technical Papers. Piscataway, NJ, USA: IEEE, 2009: 154-155.

李姝仪. HEVC中率失真算术编码与基于WPP的并行熵编码器的VLSI架构设计 [D]. 西安: 西安电子科技大学, 2017: 47-50.

VIZZOTTO B, MAZUI V, BAMPI S. Area efficient and high throughput CABAC encoder architecture for HEVC [C]∥Proceedings of the 15th IEEE International Conference on Electronics Circuits and Systems. Piscataway, NJ, USA: IEEE, 2015: 572-575.

ZHANG Yuanzhi, LU Chao. A highly parallel hardware architecture of table-based CABAC bit rate estimator in an HEVC intra encoder [J]. IEEE Transactions on Circuits and Systems for Video Technology, 2019, 29(5): 1544-1558.

TSAI S F, LI C T, CHEN H H, et al. A 1062 Mpixels/s 8192×4320p high efficiency video coding(H. 265)encoder chip [C]∥ Proceedings of the 2013 Symposium on VLSI Circuits. Piscataway, NJ, USA: IEEE, 2013: 188-189.

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