稳态视觉诱发电位脑机接口的现场可编程逻辑门阵列实现

张彦军; 谢俊; 薛涛; 曹国智; 徐光华; 李敏

doi:10.7652/xjtuxb202002020

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稳态视觉诱发电位脑机接口的现场可编程逻辑门阵列实现

更新时间：2025-05-08

- 稳态视觉诱发电位脑机接口的现场可编程逻辑门阵列实现
- Implementation of Steady-State Visual Evoked Potential BCI System Based on Field Programmable Gate Array
- 西安交通大学学报 2020年54卷第2期页码：158-165
- 作者机构：
  
  西安交通大学机械工程学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2019-07-24。作者简介: 张彦军(1994—),男,硕士生;谢俊(通信作者),男,副教授。基金项目: 国家自然科学基金资助项目(61503298)
- DOI：10.7652/xjtuxb202002020
  中图分类号： TP23
- 网络首发：2020-02-10，
  
  纸质出版：2020
- 稿件说明：
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张彦军, 谢俊, 薛涛, 等. 稳态视觉诱发电位脑机接口的现场可编程逻辑门阵列实现[J]. 西安交通大学学报, 2020,54(2):158-165.

Implementation of Steady-State Visual Evoked Potential BCI System Based on Field Programmable Gate Array[J]. 2020, 54(2): 158-165.
张彦军, 谢俊, 薛涛, 等. 稳态视觉诱发电位脑机接口的现场可编程逻辑门阵列实现[J]. 西安交通大学学报, 2020,54(2):158-165. DOI： 10.7652/xjtuxb202002020.

Implementation of Steady-State Visual Evoked Potential BCI System Based on Field Programmable Gate Array[J]. 2020, 54(2): 158-165. DOI： 10.7652/xjtuxb202002020.

摘要

针对稳态视觉诱发电位(SSVEP)脑机接口(BCI)系统对计算机性能要求较高的问题

提出一种以现场可编程门阵列(FPGA)和商用脑电采集设备为核心的SSVEP-BCI系统。该系统通过FPGA独立的显示模块

实现了视频图形矩阵(VGA)接口的控制; 按照显示刷新帧的方式分配闪烁频率对应的范式图案

实现了诱发SSVEP信号所需范式的稳定显示。通过实验对所设计的VGA视觉刺激器光闪烁频率进行采集分析可知

视觉刺激器范式显示频率与所设计的频率基本一致

可用于SSVEP诱发实验。结合所设计的视觉刺激器

完成了基于FPGA的脑电信号处理和特征识别。设计方案使用串口将脑电信号传输到FPGA端

采用快速傅里叶变换分析频率成分

对视觉刺激器对应的频率进行分析比较

最终通过实验对系统进行验证。结果表明:设计的系统在4个刺激目标和单次实验时长2 s的情况下

实现了平均85.25%的识别正确率

表明系统能够实现SSVEP信号的诱发和有效识别

并且能够达到较好的效果。

Abstract

To solve the problem that the steady-state visual evoked potential(SSVEP)brain-computer interface(BCI)system requires high computer performance

a SSVEP BCI system based on field programmable gate array(FPGA)and commercial electroencephalogram(EEG)acquisition device is designed by an independent display module based on FPGA. This system reali-es the control of video graphics array(VGA)interface. The paradigm patterns corresponding to different flicker frequencies are allocated according to the displaying refresh frames

and the stable display of the paradigm required to induce SSVEP signals can be achieved. Collecting and analy-ing the flicker outputs of the designed VGA visual stimulator

the presenting frequencies from the visual stimulator are approximately equal to the required frequencies and can be used for SSVEP BCI experiments. Combined with the designed visual stimulator

the FPGA based EEG signal processing and feature recognition are also implemented in this approach. EEG si

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