西安交通大学软件学院,西安,710049
网络首发:2016-02-10,
纸质出版:2016
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骆东旭 1, 李尊朝 2, 关云鹤 2, 等. 一种新型GaAs基无漏结隧穿场效应晶体管[J]. 西安交通大学学报, 2016,50(2):68-72+123.
A Novel GaAs-Based Tunnel Field-Effect Transistor Without Drain Junction[J]. 2016, 50(2): 68-72+123.
骆东旭 1, 李尊朝 2, 关云鹤 2, 等. 一种新型GaAs基无漏结隧穿场效应晶体管[J]. 西安交通大学学报, 2016,50(2):68-72+123. DOI: 10.7652/xjtuxb201602012.
A Novel GaAs-Based Tunnel Field-Effect Transistor Without Drain Junction[J]. 2016, 50(2): 68-72+123. DOI: 10.7652/xjtuxb201602012.
针对隧穿场效应晶体管开态电流较低的问题
提出了一种新型GaAs基无漏结隧穿场效应晶体管结构
并对其性能进行了研究。在该结构中
沟道和漏区采用具有相同掺杂浓度的N型InGaAs材料
实现沟道/漏区无结化
简化了制造工艺; 同时为了提高开态隧穿电流
源区采用不同于沟道的P型GaAsSb材料
实现异质源区/沟道结构。该结构能有效增大关态隧穿势垒宽度
降低泄漏电流
同时增加开态带带隧穿概率
提升开态电流
从而获得低亚阈值斜率和高开关比。仿真结果表明
在0.4 V工作电压下
该新型GaAs基无漏结隧穿场效应晶体管的开态电流为3.66 mA
关态电流为4.35×10
-13
A
开关电流比高达10
10
平均亚阈值斜率为27 mV/dec
漏致势垒降低效应值为126。
A novel GaAs-based tunnel field-effect transistor without drain junction is proposed to improve the on-state current and its performance is investigated. The transistor uses N-type InGaAs with the same doping concentration in the channel and drain to form junctionless channel/drain and to simplify the manufacture process
while P-type GaAsSb is used in the source to produce hetero junction source/channel and to increase the on-state current. The widened tunnel barrier in the off-state decreases the leakage current
and the promoted band-to-band tunneling probability in the on-state increases the driving current
so that both the low subthreshold slope and the high ratio between on-state current and off-state current are obtained. Numerical simulations show that the nov
el device achieves an on-state current of 3.66×10
-3
A
and an off-state current of 4.35×10
-13
A under 0.4 V voltage
and the ratio between on-state current and off-state current is 10
10
and that an average subthreshold slope of 27 mV/dec and a DIBL of 126 are obtained.
韩方忠. 隧穿场效应晶体管的模拟研究 [D]. 上海: 复旦大学, 2012.
NIRSCHL T, SCHAPER U, EINFELD J, et al. Impact of mask alignment on the tunneling field effect transistor(TFET)[C]∥Proceedings of the 2005 International Conference on Microelectronic Test Structures. Piscataway, NJ, USA: IEEE, 2005: 43-46.
CHOI W, LEE J, PARK B. Integration process of impact-ionization metal-oxide-semiconductor devices with tunneling field-effect-transistors and metal-oxide-semiconductor field-effect transistors [J]. Japanese Journal of Applied Physics, 2007, 46(1): 122-124.
GHOSH B, AKRAM M W. Junctionless tunnel field effect transistor [J]. IEEE Electron Device Letters, 2013, 34(5): 584-586.
ASTHANA P K, GHOSH B, GOSWAMI Y, et al. High speed and low power ultradeep submicrometer Ⅲ-Ⅴ heterojunctionless tunnel field-effect transistor [J]. IEEE Transactions on Electron Devices, 2014, 61(2): 479-486.
BARDON M G, NEVES H P. Pseudo two dimensional model for double-gate tunnel FETs considering the junctions depletion regions [J]. IEEE Transactions on Electron Devices, 2010, 57(4): 827-834.
郭维廉. 共振隧穿二极管的物理模型 [J]. 微纳电子技术, 2006(4): 167-171.
GUO Weilian. Physical model of resonant tunneling diode [J]. Micro-Nano-Electronic Technology, 2006(4): 167-171.
MOHATA D, MAYER T, DATTA S, et al. Temperature dependent characteristics of a vertical tunnel FET [J]. IEEE Electron Device Letters, 2010, 31(6): 564-566.
MIMURA T, ODANI K. GaAs microwave MOSFETs [J]. IEEE Transactions on Electron Devices, 1978, 25(6): 573-579.
HINKLE C L, SONNET A M, VOGEL E M, et al. GaAs interfacial self-cleaning by atomic layer deposition [J]. Applied Physics Letters, 2008, 92(7): 071901.
ZHU Y, HUDAIT M K. Low-power tunnel field effect transistors using mixed As and Sb based heterostructures [J]. Nanotechnology Reviews, 2013, 2(6): 637-678.
BIMBERG D, KIRSTAEDTER N, USTIONV V M, et al. InGaAs-GaAs quantum-dot lasers [J]. IEEE Journal of Selected Topics in Quantum Electronics, 1997, 3(2): 196-205.
徐会芳. 新型纳米器件的研究与建模 [D]. 合肥: 安徽大学, 2015.
PAUSSA A, PALESTRI P, GEROMEL M, et al. Simulation of the performance of graphene FETs with a semiclassical model, including band-to-band tunneling [J]. IEEE Transactions on Electron Devices, 2014, 61(5): 1567-1574.
SYNOPSYS Corporation. Sentaurus device user guide [EB/OL].(2010-10-13)[2015-04-23]. http: ∥www. docin.com/p-351831400.html.
SCHENK A. A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon [J]. Solid-State Electronics, 1992, 35(11): 1585-1596.
HANSCH W, KIRCHNER R, VOGLSANG T, et al. Carrier transport near the Si/SiO2 interface of a MOSFET [J]. Solid-State Electronics, 1989, 32(10): 839-849.
KUMAR M J, SIVA M. The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs [J]. IEEE Transactions on Electron Devices, 2008, 55(6): 1554-1557.
MOHATA D K. Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300 mV logic applications [C]∥ Proceedings of IEEE International Electron Devices Meeting. Piscataway, NJ, USA: IEEE, 2011: 33-37.
BRESSON N, CRISTO S, LWAI H, et al. Integration of buried insulators with high thermal conductivity in SOI MOSFETs: thermal properties and short channel effects [J]. Solid-State Electronics, 2005, 49(9): 1522-1528.
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