一种超低功耗的低压差线性稳压器环路补偿方法

刘晨 1; 2; 来新泉 1; 钟龙杰 1; 杨伟 1

doi:10.7652/xjtuxb201601021

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一种超低功耗的低压差线性稳压器环路补偿方法

更新时间：2025-07-09

- 一种超低功耗的低压差线性稳压器环路补偿方法
- A Loop Compensation Method of Low Dropout Regulator with Ultra Low Power
- 西安交通大学学报 2016年50卷第1期页码：139-144
- 作者机构：
  
  1. 西安电子科技大学CAD研究所,西安,710071
  2. 空军工程大学防空反导学院,西安,710051
- 作者简介：
- 基金信息：
  
  : 2015-06-03。作者简介: 刘晨(1977—),男,博士生;来新泉(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(61106026);中央高校基本科研业务费资助项目(JB150222)
- DOI：10.7652/xjtuxb201601021
  中图分类号： TN911.7
- 网络首发：2016-01-10，
  
  纸质出版：2016
- 稿件说明：
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刘晨 1, 2, 来新泉 1, 等. 一种超低功耗的低压差线性稳压器环路补偿方法[J]. 西安交通大学学报, 2016,50(1):139-144.

A Loop Compensation Method of Low Dropout Regulator with Ultra Low Power[J]. 2016, 50(1): 139-144.
刘晨 1, 2, 来新泉 1, 等. 一种超低功耗的低压差线性稳压器环路补偿方法[J]. 西安交通大学学报, 2016,50(1):139-144. DOI： 10.7652/xjtuxb201601021.

A Loop Compensation Method of Low Dropout Regulator with Ultra Low Power[J]. 2016, 50(1): 139-144. DOI： 10.7652/xjtuxb201601021.

摘要

针对低压差线性稳压器(LDO)电路设计中为改善环路补偿的稳定性增加电流缓冲电路而带来额外功耗的问题

提出一种嵌入式LDO环路补偿方法。该方法在原LDO的误差放大器模块中

嵌入一个由晶体管和电容组成的电流缓冲电路

该结构与误差放大器的共源共栅输出级共用晶体管

由于整体电路中不增加新元器件

因此消除了引入缓冲电路所带来的额外功耗。仿真实验验证了加入电流缓冲电路后系统环路稳定性能得到了改善。采用联华电子公司0.5 μm 5 V的CMOS工艺线在LDO中进行了投片验证

实测芯片静态功耗电流仅为50 μA

当输入电压从3 V跳变到5 V时

输出电压的上冲与下冲都小于15 mV

负载电阻从18 kΩ跳变到9 Ω时

输出电压的最大变化小于20 mV。投片测试结果表明

该补偿方法可在提高系统环路稳定性的同时消除额外功耗。

Abstract

An embedded loop compensation method of LDO is proposed to solve the problem that the current buffer technique overcomes the drawback of traditional miller compensation

but consumes extra power. It merges the current buffer into the fold-back amplifier

so that the LDO circuit and the current buffer circuit share the transistor

and the loop stability of the circuit can be improved without adding the components. The principle of the proposed compensation method is analyzed and described in detail. The method is tested in a low-dropout voltage regulator using UMC 0.5 μm 5 V CMOS technology

and the results show that chip static power current has only 50 μA

and both the output voltage overshoot and undershoot are below 15 mV when the input voltage changes from 3 V to 5 V. The maximum change of the output voltage is less than 20 mV when the load resistance reduces from 18 kΩ to 9 Ω. The measurement results show that the embedded structure eliminates the extra power loss and improves loop stability.

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references

毕查德·拉扎维. 模拟CMOS集成电路设计 [M]. 西安: 西安交通大学出版社, 2003: 303-305.

张显库, 袁杨. 具有不稳定零极点对消的结构图等效问题 [J]. 计算技术与自动化, 2010, 29(3): 6-8.

ZHANG Xianku, YUAN Yang. Problem of block diagram algebra with unstable pole-zero cancellation [J]. Computing Technology and Automation, 2010, 29(3): 6-8.

BLAKIEWICZ G. Output-capacitor less low-dropout regulator using a cascoded flipped voltage follower [J]. IET Circuits Devices Systems, 2011, 5(5): 418-423.

AHUJA B K. An improved frequency compensation technique for CMOS operational amplifiers [J]. IEEE Journal of Solid-State Circuits, 1983, 18(6): 629-633.

RAJPUT S K, HEMANT B K. Two-stage high gain low power OpAmp with current buffer compensation [C]∥Proceedings of 2013 Global High Tech Congress on Electronics. Piscataway, NJ, USA: IEEE, 2013: 121-124.

ZABRODA O, MURMANN B. Eliminating complex conjugate poles in two-stage operational amplifiers with current buffer Miller compensation [J]. Analog Integration Circuit Signal Process, 2014, 81(2): 361-365.

WANG Wei, YAN Zushu, MAK P I. Micropower two-stage amplifier employing recycling current-buffer Miller compensation [C]∥Proceedings of 2014 IEEE International Symposium on Circuits and Systems. Piscataway, NJ, USA: IEEE, 2014: 1889-1892.

陈颖玉, 郑金棋, 王慧贞. 一种新型大功率无损缓冲Buck变换器的研究 [J]. 电力电子技术, 2015, 49(6): 94-98.

CHEN Yingyu, ZHENG Jinqi, WANG Huizhen. Research on a novel high-power buck converter using loss-less snubber [J]. Power Electronics, 2015, 49(6): 94-98.

SANSEN W M C. Analog design essentials [M]. Berlin, Germany: Springer Inc., 2006: 102-105.

GRAY P R, MEYER R G. MOS operational amplifier design: a tutorial overview [J]. IEEE Journal of Solid-State Circuits, 1982, 17(6): 969-982.

GARIMELLA A, FURTH P M, SURKANTI P R. Current buffer compensation topologies for LDOs with improved transient performance [J]. Analog Integrated Circuits and Signal Processing, 2012, 73(1): 131-142.

AL-SHYOUKH M, LEE H, PEREZ R. A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation [J]. IEEE Journal of Solid-State Circuits, 2007, 42(8): 1732-1742.

BRIAN M K. Understanding the load-transient response of LDOs [J]. Analog Applications Journal, 2000(9): 19-23.

YEONG T L, CHI C U, MEI C J. A low dropout regulator using current buffer compensation technique [C]∥Proceedings of 2010 International Conference on Solid-State and Integrated Circuit Technology. Piscataway, NJ, USA: IEEE, 2010: 144-146.

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