An improved architecture of combining 2.5 b/stage and 1.5 b/stage structures is presented to solve the problem that high speed

high precision and dynamic specification are concerned at the same time in pipelined analog-to-digital converters(ADC). In the system

2.5 b/stage structure is applied in the first stage

and 1.5 b/stage structures are applied in 2 to 10 stages

which extends the dynamic range of the system

modularizes the design and decreases the complexity of circuits. Two-stage Bicmos operational amplifier and a novel differential comparator that is used in 1.5 b/stages are designed. The operational amplifier can achieve high gain

bandwidth

fast speed

output swing at the same time

does not need compensation capacitance

and could operate in high frequency environment. The comparator does not need resistances to produce reference voltage

decreases the number of devices and saves chip area. The ADC is designed with 0.35 μm Bicmos process and 3.3 V power supply. The simulation results show that the SNR of system is 73.7 dB

the effective number of bits is 11.95 b

and spurious free dynamic range is 87.4 dB in 100 MHz sampling rate environment. The ADC can achieve 12 b converter precision when the sampling rate is 100 MHz.