Radix-8复数除法器的设计与实现

王东 1; 郑南宁 1; Milo D. ERCEGOVAC 2

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Radix-8复数除法器的设计与实现

更新时间：2025-07-09

- Radix-8复数除法器的设计与实现
- Design and Implementation of Radix-8 Complex Divider
- 西安交通大学学报 2009年43卷第10期页码：1-6
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2009-04-10. 作者简介: 王东(1981-),男,博士生;郑南宁(联系人),男,教授,博士生导师,中国工程院院士. 基金项目: 国家基础研究发展规划资助项目(2007CB311005);国家高技术研究发展计划资助项目(2009AA01Z307,2006AA01Z192,2006AA01Z318);国家留学基金委资助项目(2008628039)
- DOI：
  中图分类号： TP332
- 网络首发：2009-10-10，
  
  纸质出版：2009
- 稿件说明：
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王东 1, 郑南宁 1, Milo D. ERCEGOVAC 2. Radix-8复数除法器的设计与实现[J]. 西安交通大学学报, 2009,43(10):1-6.

Design and Implementation of Radix-8 Complex Divider[J]. 2009, 43(10): 1-6.
王东 1, 郑南宁 1, Milo D. ERCEGOVAC 2. Radix-8复数除法器的设计与实现[J]. 西安交通大学学报, 2009,43(10):1-6. DOI：

Design and Implementation of Radix-8 Complex Divider[J]. 2009, 43(10): 1-6. DOI：

摘要

设计了一种高性能、低功耗的Radix-8时序复数除法器.该复数除法器采用了逐位递归算法和操作数预变换技术

并在传统结构的基础上

选用冗余形式保留预校正变量

节省了超长进位加法器的使用

缩短了关键路径的延时.设计还通过实部和虚部商位的合并以及基于6输入查找表结构的硬件优化

提高了乘加逻辑单元的资源利用率.Stratix-II型现场可编程逻辑器件仿真验证表明

与使用超长进位加法器的传统结构相比

所设计的复数除法器的速度提高了44%

硬件资源减少了31%.

Abstract

A Radix-8 complex divider with high performance and low power is designed. The complex divider architecture adopts the digit-recurrence algorithm and the prescaling technique of operands

and has an optimizing function

with which the prescaled operands are kept in redundant forms so that long carry propagation adders are saved. Moreover

combination of the real and imaginary parts of the internal quotient digits and optimization for hardware mapping based on the 6-input look-up table are made to improve the utilization of logic resources. The proposed design is then implemented on Stratix-II field programmable gate array. Simulation results and comparisons with the traditional structure show that the speed of the complex divider is increased by 44% and its hardware resources are reduced by 31%.

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references

XIANG Jianhong, GUO Lili, CHEN Ying,et al. Study of GPS adaptive antenna technology based on complex number AACA [C]∥Proceedings of IEEE International Conference on Wireless Communications, Networking and Mobile Computing. Piscataway,NJ, USA: IEEE, 2008: 1-4.

EDMAN F, OWALL V. Compact matrix inversion architecture using a single processing element [C]∥Proceedings of IEEE International Conference on Electronics, Circuits and Systems. Piscataway, NJ, USA: IEEE, 2005: 1-4.

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LIU Jie, WEAVER B, ZAKHAROV Y. FPGA implementation of multiplication-free complex division [J]. Electronic Letters, 2008,44(2): 95-96.

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ERCEGOVAC M, LANG T. Division and square root: digit-recurrence algorithms and implementations[M]. Bostons, MA,USA: Kluwer Academic Publishers, 1994.

LEWIS D. The Stratix-II logic and routing architecture[C]∥Proceedings of International Symposium on Field Programmable Gate Arrays. Piscataway, NJ, USA: IEEE, 2005: 14-20.

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WANG Dong, ERCEGOVAC M. Design and FPGA implementation of complex fixed-point dividers [EB/OL].(2009-03-25)[2009-04-01].http:∥fmdb. cs.ucla. edu/Treports/090032,pdf.

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