Lingappan L, Ravi S, Jha N K. Satisfiability-based test generation for nonseparable RTL controller-datapath circuits [J]. IEEE Trans on CAD, 2006, 25(3): 544-557.

Mourad S. Principle of testing electronic systems [M]. New York: John Wiley Sons, Inc., 2000.

Bushnell L M, Vishwani D A. Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits [M]. Dordrecht, Netherlands: Kluwer Academic Publishers, 2000.

Amyeen M E, Fuchs W K, Pomeranz I, et al. Fault equivalence identification in combinational circuits using implication and evaluation techniques [J]. IEEE Trans on CAD, 2003, 22(7): 922-936.

Dwarakanath K N, Blanton R D. Exploiting dominance and equivalence using fault tuples [C]∥Proc 20th IEEE VLSI Test Symposium. Los Alamitos, USA: IEEE CS Press, 2002:269-274.

Stephan P, Brayton R, Sangiovanni A. Combinational test generation using satisfiability [J]. IEEE Trans on CAD, 1996, 15(8):1167-1176.

Junhao S, Görschwin F, Drechsler R, et al. PASSAT: efficient SAT-based test pattern generation for industrial circuits [C]∥Proc IEEE Computer Society Annual Symposium on VLSI. Los Alamitos, USA: IEEE CS Press, 2005: 212-217.

Yang K, Cheng K T, Wang L C. TranGen: a SAT-based ATPG for path-oriented transition faults [C]∥IEEE Proc ASP-DAC 2004. Los Alamitos, USA: IEEE CS Press, 2004: 92-97.

Kameshwar C, Michael S H. Decision selection and learning for an ‘all-solutions ATPG engine [C]∥Proceedings of International Test Conference. Los Alamitos, USA: IEEE CS Press, 2004: 607-616.

Lintao Z, Madigan C F, Moskewicz M H, et al. Efficient conflict driven learning in a Boolean satisfiability solver [C]∥IEEE/ACM International Conference on Computer Aided Design. Los Alamitos, USA: IEEE CS Press, 2001: 279-285.

Sheng S, Hsiao M S. Success-driven learning in ATPG for preimage computation [J]. IEEE Design Test of Computers, 2004, 21(6): 504-512.