硅基完全集成DC/DC 转换器中多层平面电感设计与建模

李清华; 邵志标; 耿莉

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硅基完全集成DC/DC 转换器中多层平面电感设计与建模

专题研究 | 更新时间：2025-12-08

- 硅基完全集成DC/DC 转换器中多层平面电感设计与建模
- Design and Modeling of Multi-Layer Planar Inductor for Fully Integrated DC/DC Converters on Silicon Substrate
- 西安交通大学学报 2007年41卷第4期页码：463-466
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
  
  : 2006-09-06. 作者简介: 李清华(1976～),女,博士生;邵志标(联系人),男,教授,博士生导师. 基金项目: 国家自然科学基金资助项目(60206003)
- DOI：
  中图分类号： TN4
- 网络首发：2007-04-10，
  
  纸质出版：2007
- 稿件说明：
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李清华, 邵志标, 耿莉. 硅基完全集成DC/DC 转换器中多层平面电感设计与建模[J]. 西安交通大学学报, 2007,41(4):463-466.

李清华, 邵志标, 耿莉. Design and Modeling of Multi-Layer Planar Inductor for Fully Integrated DC/DC Converters on Silicon Substrate[J]. 2007, 41(4): 463-466.
李清华, 邵志标, 耿莉. 硅基完全集成DC/DC 转换器中多层平面电感设计与建模[J]. 西安交通大学学报, 2007,41(4):463-466. DOI：

李清华, 邵志标, 耿莉. Design and Modeling of Multi-Layer Planar Inductor for Fully Integrated DC/DC Converters on Silicon Substrate[J]. 2007, 41(4): 463-466. DOI：

摘要

为提高完全集成低压低功率DC/DC转换器转换效率与输出电流能力

提出了一种多层混联螺旋电感结构.该结构基于标准0.5 μm 2P3M CMOS工艺

将下面较薄的两层金属线圈多点并联

再与最上层金属线圈串联.多点并联结构有效地增加了等效金属层的厚度

串联结构增加了线圈之间的互感值

从而可以在不增加额外工艺成本的条件下显著提高平面电感的品质因数、单位面积电感值和电感线圈的电流承受能力.所提出的模型为完全集成DC/DC转换器的整体电路模拟分析提供了便利基础.基于0.5 μm 2P3M CMOS硅衬底工艺的模拟计算结果表明

在DC/DC转换器工作频段50～400 MHz

取得了预期电感的设计效果

最大品质因数值达4.2

单位面积电感值达到83 mH/m

可以承受的电流达90 mA.电感芯片测试结果与模型模拟结果基本吻合.

Abstract

In order to improve the conversion efficiency and output current carrying capability of the fully integrated low voltage and low power DC/DC converters

a series parallel multi-layer spiral inductor based on standard 0.5 μm 2P3M CMOS technology was proposed. The paralleled metals contacted by vias array increased the effective metal thickness and the series metals increased the mutual inductance between the layers. Therefore

the quality factor

the inductance in unit area and the current handling capability of the series parallel inductors were observably improved without extra technology. The developed model provides whole circuit analog analysis of fully integrated DC/CD converters with convenient basis. Closed form expressions of lumped parameters were obtained and verified with 0.5 μm CMOS silicon technology. Experiment results show that the maximum quality factor is 4.2

the inductance in unit area is 83 nH per square millimeter

and the handled current is 90 mA. The model agrees well with measurements in the interesting frequency band

from 50 MHz to 400 MHz.

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references

Musunuri S, Chapman P L, Zou J, et al.Design issues for monolithic DC-DC converters [J]. IEEE Transactions on Power Electronics,2005,20(3): 639-649.

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Erickson R W, Maksimovic D. Fundamentals of power electronics [M]. 2nd ed.Norvell:Kluwer Academic Publishers,2001:15-27.

Li Qinghua, Geng Li, Shao Zhibiao.Optimum double-layer spiral inductor on silicon substrate designed for monolithic buck converters [C]∥Proc of 17th Asia-Pacific Microwave Conference.Piscataway, USA: IEEE, 2005:2156-2159.

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