运用电路蕴涵及拓扑信息提高数字电路故障压缩效率

胡晓菁; 宋政湘; 王建华; 耿英三; 申望

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运用电路蕴涵及拓扑信息提高数字电路故障压缩效率

专题研究 | 更新时间：2025-12-08

- 运用电路蕴涵及拓扑信息提高数字电路故障压缩效率
- Fault Collapsing Efficiency Improvement in Digital Circuits with Implication and Topological Information
- 西安交通大学学报 2008年42卷第8期页码：958-962
- 作者机构：
  
  西安交通大学电力设备电气绝缘国家重点实验室,西安,710049
- 作者简介：
- 基金信息：
  
  : 2007-09-06. 作者简介: 胡晓菁(1980-),女,博士生;王建华(联系人),男,教授,博士生导师. 基金项目: 新世纪优秀人才支持计划资助项目(NCET070675)
- DOI：
  中图分类号： TN407;TP391.7
- 网络首发：2008-08-10，
  
  纸质出版：2008
- 稿件说明：
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胡晓菁, 宋政湘, 王建华, 等. 运用电路蕴涵及拓扑信息提高数字电路故障压缩效率[J]. 西安交通大学学报, 2008,42(8):958-962.

胡晓菁, 宋政湘, 王建华, et al. Fault Collapsing Efficiency Improvement in Digital Circuits with Implication and Topological Information[J]. 2008, 42(8): 958-962.
胡晓菁, 宋政湘, 王建华, 等. 运用电路蕴涵及拓扑信息提高数字电路故障压缩效率[J]. 西安交通大学学报, 2008,42(8):958-962. DOI：

胡晓菁, 宋政湘, 王建华, et al. Fault Collapsing Efficiency Improvement in Digital Circuits with Implication and Topological Information[J]. 2008, 42(8): 958-962. DOI：

摘要

为提高数字电路故障诊断的效率

针对传统故障压缩算法的压缩率不高、计算复杂的问题

提出新的解决方法.与传统方法不同

该方法通过对故障检测函数的分析得出决定电路中特殊结构的故障关系规律.首先利用电路蕴涵信息推导出电路中节点与其支配点之间故障等价与支配关系

随后总结出具有重汇聚扇出源与其分支之间故障关系的规律

故障关系与扇出分支的反向奇偶特性密切相关

并且受重汇聚节点逻辑功能影响

进而发展为运用电路蕴涵及拓扑信息来压缩故障的方法.基于ISCAS85 Benchmark 的实验结果表明

该方法可有效判断出电路中可测故障的等价与支配关系

并且实现简单

计算量较小.

Abstract

To improve the efficiency of fault diagnosis in digital circuits

a novel method is proposed to solve inefficient compacting and complex computing in the traditional algorithms. Compared with traditional method

the rules that determine fault relations in special structure are summarized by analyzing fault detect function. The equivalence and dominance fault between node and its dominator with implications are identified

then the fault equivalence and dominance rule for reconvergent fan-out stem and branches is also found out

which is not only depended on topological structure in circuit

namely

inversion parity of branches

but also influenced by logic function of reconvergent point. Moreover

the fault collapsing method using implication and topological information is presented. The experimental results based on ISCAS85 benchmark show that this method enables to identify equivalence and dominance fault in circuit effectively with a slight computation task.

关键词

Keywords

references

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CHEN J E, LEE C L, SHEN W Z, et al. Fanout fault analysis for digital logic circuits[C]∥Proceedings of the Fourth Asian Test Symposium. Los Alamitos, USA: IEEE Computer Science Society Press, 1995: 33-39.

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