A write coalescing design for write-through cache is proposed to promote the performance of application processors using on-chip buffer. The scheme of write coalition for the local data in the same row of SDRAM(synchronous dynamic random access memory)is designed to improve accessing efficiency by employing the single write mode of SDRAM and on-chip buffer. A coherence scheme for the single or multiple cache data reading or writing is also presented. Simulation for mp3 decoding data is implemented in the RTL(register transmit language)simulation environment for Leon2 processor. The simulation results show that when the on-chip buffers are optimized at 3 rows and 8 columns

average 7.8 words are written into the SDRAM after every row pre-charge

and the accessing efficiency increases from 12% to 19% at 100 MHz

and that the area of the proposed design is 0.263 mm

2

under TSMC 0.

18 μm process.