A 16 Gb/s SerDes Transmitter for High-Speed and High-Precision Analog-to-Digital Convertors

HAN Jiali; REN Jiajia; PEI Lei; LI Nannan; QI Huanhuan; WANG Jinfu; ZHANG Jie; ZHANG Hong

doi:10.7652/xjtuxb202409017

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A 16 Gb/s SerDes Transmitter for High-Speed and High-Precision Analog-to-Digital Convertors

更新时间：2025-07-28

- A 16 Gb/s SerDes Transmitter for High-Speed and High-Precision Analog-to-Digital Convertors
- Vol. 58, Issue 9, Pages: 173-182(2024)
- 作者机构：
  
  1. 西安交通大学微电子学院,西安,710049
  2. 西安航天民芯科技有限公司,西安,710076
- 作者简介：
- 基金信息：
- DOI：10.7652/xjtuxb202409017
  CLC： TN432
- Online First：10 September 2024，
  
  Published：2024
- 稿件说明：
移动端阅览
HAN Jiali, REN Jiajia, PEI Lei, et al. A 16 Gb/s SerDes Transmitter for High-Speed and High-Precision Analog-to-Digital Convertors[J]. 2024, 58(9): 173-182.
DOI：

HAN Jiali, REN Jiajia, PEI Lei, et al. A 16 Gb/s SerDes Transmitter for High-Speed and High-Precision Analog-to-Digital Convertors[J]. 2024, 58(9): 173-182. DOI： 10.7652/xjtuxb202409017.

摘要

针对高速高精度模数转换器(ADC)中的高速串行接口(SerDes)发射机电路面临的信道损耗、噪声、串扰、工艺波动等非理想因素

提出了一种符合传输接口JESD204B协议要求的高速串行发射机电路结构

综合使用匹配阻抗校准、前馈均衡(FFE)和T-coil等技术来改善数据传输质量。对于现有半速率发射机结构对时钟占空比较为敏感的问题

设计了时钟占空比校准电路来稳定输出时钟的占空比。另外

文中所采用的多支路并联的源串联终端(SST)驱动器架构

有效地实现了匹配阻抗校准与前馈均衡方案的结合

大幅减小了电路复杂度和面积占用

显著降低了发射机功耗。提出的发射机电路采用28 nm CMOS工艺设计并流片

实测结果表明

在16 Gb/s的传输速率下

输出信号眼高为811 mV、眼宽约为58.8 ps

总抖动为7.35 ps

发射机功耗约为49.2 mW

能效比为3.07 pJ/bit

电路版图面积约为300×150 μm

。在满足协议要求的前提下

该发射机在抖动性能、能效和电路面积上具有显著优势。

Abstract

A high-speed serial transmitter circuit compliant with the JESD204B protocol is designed in this paper

aiming to address the non-ideal factors such as channel attenuation

noise

and crosstalk faced by the transmitter circuit of high-speed Serial/De-serial interface(SerDes)in high-speed and high-precision analog-to-digital converters(ADCs). The design employs several techniques such as matching impedance calibration

feed-forward equalization

and T-coil to improve the quality of data transmission. In addition

to tackle th

e sensitivity of the current half-rate transmitter architecture to variation in the input clock duty cycle

a duty cycle calibration circuit is devised to stabilize the duty cycle of the output clock. Besides

the source-series-terminated(SST)driver architecture with multiple parallel slices is adopted to realize the combination of matching impedance calibration and feed-forward equalization scheme

significantly reducing circuit complexity

area occupation

and power consumption of the transmitter. The transmitter is designed and fabricated in a 28 nm CMOS process. Measurement results show that

at a transmission rate of 16 Gb/s

the transmitter achieves an eye height of 811 mV

an eye width of 58.8 ps

a total jitter of 7.35 ps

a power consumption of 49.2 mW

and an energy efficiency rate of 3.07 pJ/bit. The layout area measures 300×150 μm

. The transmitter showcases significant advantages in terms of jitter performance

energy efficiency

and circuit area while meeting protocol requirements.

关键词

Keywords

references

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