Memory-Efficient Architecture of 2-D Discrete Wavelet Transform

doi:10.7652/xjtuxb202201020

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Memory-Efficient Architecture of 2-D Discrete Wavelet Transform

更新时间：2025-05-08

- Memory-Efficient Architecture of 2-D Discrete Wavelet Transform
- Vol. 56, Issue 1, Pages: 177-183(2022)
- 作者机构：
  
  天津大学微电子学院,天津,300072
- 作者简介：
- 基金信息：
- DOI：10.7652/xjtuxb202201020
  CLC： TN47
- Online First：10 January 2022，
  
  Published：2022
- 稿件说明：
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Memory-Efficient Architecture of 2-D Discrete Wavelet Transform[J]. 2022, 56(1): 177-183.
DOI：

Memory-Efficient Architecture of 2-D Discrete Wavelet Transform[J]. 2022, 56(1): 177-183. DOI： 10.7652/xjtuxb202201020.

摘要

针对二维9/7离散小波变换硬件架构中数据缓存需求高的问题

提出了一种基于提升算法的低存储架构。通过调整提升算法数据计算顺序

设计了一种动态计算二维小波变换的新型迭代分步计算方法。根据行、列变换的不同

对其分别做一维变换架构设计

其中行滤波器结构通过将输入数据进行三序列分裂

有效减少了寄存器数; 列滤波器结构通过单行输入处理消除转置存储器

同时实现了乘法器和加法器的复用。整体二维变换采用并行和流水线混合架构设计

关键路径延时减小到一个乘法器延迟。实验结果表明

对于1 024像素×1 024像素的图像

与其他提升结构相比

本结构片上内存使用减少了11.1%

硬件效率提高了8.2%以上; 与基于卷积的迭代计算方法相比

计算周期减少为现有结构的1/9。在型号为Xilinx Kintex7 XC7K325T的现场可编程逻辑门阵列上实现

吞吐率达到460 MB/s

且具有明显的硬件资源优势。

Abstract

In the two-dimensional 9/7 discrete wavelet transform hardware architecture

high data storage requirements is always the problem to be solved. A lifting-based memory-efficient architecture is proposed. First

the data calculation sequence of the lifting algorithm is modified

and a new iterative step-by-step calculation method is designed to dynamically calculate the two-dimensional wavelet transform. According to the difference of row and column transforms

one-dimensional transform architecture design is performed on them. The row filter structure effectively reduces the number of registers by splitting the input data into three sequences. The column filter structure eliminates the data buffer of the transposed module through single-line input processing. At the same time

the multiplexing of multipliers and adders is realized. With parallel and pipeline hybrid architecture

the critical path delay of two-dimensional transform structure is reduced to a multiplier delay. Experimental results show that for an image of 1 024 pixel × 1 024 pixel

the on-chip memory requirement is reduced by 11.1%

and the hardware efficiency is raised by 8.24% in contrast to the existing lifting-based architectures. Compared with the iterative calculation method based on convolution

the calculation time is reduced to 1/9 of the existing structure. The proposed architecture is implemented on Xilinx FPGA Kintex7 XC7K325T

achieving a throughput of 460 MB/s and obvious hardware resource advantages.

关键词

Keywords

references

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