A High-Throughput Parallel Very-Large-Scale Integration Architecture of Entropy Coding in High Efficiency Video Coding[J]. 2020, 54(7): 180-186.
DOI:
A High-Throughput Parallel Very-Large-Scale Integration Architecture of Entropy Coding in High Efficiency Video Coding[J]. 2020, 54(7): 180-186.DOI: 10.7652/xjtuxb202007021.
A High-Throughput Parallel Very-Large-Scale Integration Architecture of Entropy Coding in High Efficiency Video Coding
Due to the real-time requirements of ultra-high-definition video encoding and the data throughput bottleneck in the entropy encoding system
a hardware architecture based on wavefront parallel processing(WPP)technology is proposed
which improves the parallelism of coding while retaining row-to-row dependency
and provides higher throughput and compression efficiency. This architecture allows three-threaded coding tree units to be encoded simultaneously
thus improves the parallelism by nearly three times. The synchronous update unit ensures the probability models between threads can be updated simultaneously. The probability models in a single thread support parallel updating of multiple binary symbols. Initiali-ation unit can initiali-e the coding units in multiple modes. Online mode and offline mode are both supported
which can balance the throughput between entropy encoder and other modules. This entropy encoder delivers an average of 5 b per cycle. The design is synthesi-ed in SM
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references
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