Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors

doi:10.7652/xjtuxb202005015

您当前的位置：

首页 >

文章列表页 >

Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors

更新时间：2025-07-09

- Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors
- Vol. 54, Issue 5, Pages: 109-116(2020)
- 作者机构：
  
  西安交通大学微电子学院,西安,710049
- 作者简介：
- 基金信息：
- DOI：10.7652/xjtuxb202005015
  CLC： TN432
- Online First：10 May 2020，
  
  Published：2020
- 稿件说明：
移动端阅览
Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors[J]. 2020, 54(5): 109-116.
DOI：

Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors[J]. 2020, 54(5): 109-116. DOI： 10.7652/xjtuxb202005015.

摘要

针对现有高速高精度模数转换器(ADC)芯片内部参考电压缓冲器需要牺牲很大功耗来满足精度和速度要求的问题

提出了一种具有非对称AB类输出级的全差分参考电压缓冲器

能够以较低的运放增益满足缓冲器高精度的需求

从而显著降低缓冲器的功耗。通过引入非对称的输出结构

参考电压缓冲器只需要满足高带宽

不再需要较高的开环增益; 输入级采用互补结构进一步降低了功耗; 为了消除传统结构所引入的高阻节点

提出了低输出阻抗的AB类驱动电路

提高了带宽。仿真结果表明

在负载为20 pF的片内滤波电容的情况下

参考电压缓冲器的功耗为27 mW

建立时间小于2.5 ns

与相近性能的电路相比

所提电路的功耗更低。其中运放的单位增益带宽为602 MHz

相位裕度为61°。所提出的参考电压缓冲器应用于一款双通道14位200 MHz的流水线ADC中

测试结果表明

ADC的信号噪声失真比达到73 dB

所提出的电路结构能以较低的功耗实现较高的精度和速度。

Abstract

For solving the problem that the internal reference voltage buffer of high-speed analog-to-digital converter(ADC)has to consume large power to achieve high accuracy and high sampling rate

a fully differential reference voltage buffer with an asymmetric class-AB output stage is presented. The voltage buffer achieves high precision with a relatively low op-amp gain

which significantly reduces the power consumption of the buffer. By introducing an asymmetric output structure

the circuit only needs to satisfy large bandwidth but no longer needs a high open-loop gain

and the input stage uses a complementary structure to further reduce power consumption. A class-AB driving circuit with low output impedance eliminates the high-resistance nodes introduced by the common structure and increases the bandwidth. Simulation results show that the power consumption of this reference voltage buffer is 27 mW and the settling time is less than 2.5 ns when driving a 20 pF on-chip filtering capacitor

关键词

Keywords

references

贾华宇, 陈贵灿, 程军, 等. 流水线模数转换器的一种数字校准技术 [J]. 西安交通大学学报, 2008, 42(8): 991-995.

JIA Huayu, CHEN Guican, CHENG Jun, et al. A digital calibration technique of pipelined analog to digital converter [J]. Journal of Xi’an Jiaotong University, 2008, 42(8): 991-995.

张鸿, 陈贵灿, 程军, 等. 流水线模数转换器中高速低功耗开环余量放大器的设计 [J]. 西安交通大学学报, 2008, 47(7): 1585-1593.

ZHANG Hong, CHEN Guican, CHENG Jun, et al. Low power and high speed open-loop residue amplifier for pipelined analog-to-digital converters [J]. Journal of Xi’an Jiaotong University, 2008, 42(6): 751-755.

张鸿, 张牡丹, 张杰, 等. 用于植入式医疗装置的逐次逼近式模数转换器 [J]. 西安交通大学学报, 2015, 49(2): 43-48.

ZHANG Hong, ZHANG Mudan, ZHANG Jie, et al. A successive approximation register analog-to-digital converter for implantable biomedical device [J]. Journal of Xi’an Jiaotong University, 2015, 49(2): 43-48.

陈浩, 孙权, 张鸿, 等. 用于超低频信号测量的高精度低功耗增量式模数转换器 [J]. 西安交通大学学报, 2017, 51(6): 79-85.

CHEN Hao, SUN Quan, ZHANG Hong, et al. Incremental analog-to-digital converter with high resolution and low power for measurement of ultra-low-frequency signals [J]. Journal of Xi’an Jiaotong University, 2017, 51(6): 79-85.

王玉伟, 张鸿, 张瑞智. 一种超低功耗的低电压全金属氧化物半导体基准电压源 [J]. 西安交通大学学报, 2017, 51(8): 47-52.

WANG Yuwei, ZHANG Hong, ZHANG Ruizhi. A low-voltage all metal oxide semiconductor voltage reference with ultra-low power [J]. Journal of Xi’an Jiaotong University, 2017, 51(8): 47-52.

MOHAMED E, AMER A, TORRES J, et al. High PSR low drop-out regulator with feed-forward ripple cancellation technique [J]. IEEE Journal of Solid-State Circuits, 2010, 45(3): 565-577.

LEE C K, KIM W, KANG H, et al. A replica-driving technique for high performance SC circuits and pipelined ADC design [J]. IEEE Transactions on Circuits and Systems: II Express Briefs, 2013, 60(9): 557-561.

HARIKUMAR P, WIKNER J J. Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS [C]∥Proceedings of the IEEE International Symposium on Circuits and Systems. Piscataway, NJ, USA: IEEE, 2015: 249-252.

陈珍海, 于宗光. 用于16 bit 100 MS/s ADC的高精度参考电压产生电路 [J]. 西安电子科技大学学报, 2017, 44(3): 127: 133.

CHEN Zhenhai, YU Zongguang. High precision voltage reference generator for 16-bit 100 MS/s ADC [J]. Journal of Xidian University, 2017, 44(3): 127-133.

CAI Hua, LI Ping. A CMOS switch-capacitor 14-bit 100 Msps pipeline ADC with over 90 dB SFDR [J]. International Journal of Electronics, 2012, 100(1): 1-10.

CAI Hua. A low-power, fast-settling reference circuit for high-speed high-resolution ADC [J]. International Journal of Electronics, 2014, 101(4): 492-499.

WOLFER S, COMER D T, COMER D J. A high speed, precision voltage buffer in a submicron CMOS process [J]. International Journal of Electronics, 2000, 87(12): 1443-1452.

尹勇生, 杨鑫波, 邓红辉. 应用于高速高精度流水线ADC中的差分参考源 [J]. 电子测量与仪器学报, 2012, 26(12): 1043-1049.

YIN Yongsheng, YANG Xinbo, DENG Honghui. A differential reference voltage source used in high-speed high-precision pipelined ADC [J]. Journal of Electronic Measurement and Instrument, 2012, 26(12): 1043-1049.

HARIKUMAR P, ANGELOV P, HAGGLUND R. Design of a reference voltage buffer for a 10-bit 1-MS/s SAR ADC [C]∥Proceedings of the 21st International Conference on Mixed Design of Integrated Circuits and Systems. Piscataway, NJ, USA: IEEE, 2014: 249-252.

ZHANG Jie, ZHANG Hong, SUN Quan, et al. A low-noise, low-power amplifier with current-reused OTA for ECG recordings [J]. IEEE Transactions on Biomedical Circuits and Systems, 2018, 12(3): 700-708.

ZHANG Fan, HOLLEMAN J, OTIS B P. Design of ultra-low power biopotential amplifiers for biosignal acquisition applications [J]. IEEE Transactions on Biomedical Circuits and Systems, 2012, 6(4): 344-355.

CANNIZZARO S O, PALUMBO G, PENNISI S. Accurate estimation of high-frequency harmonic distortion in two-stage miller OTAs [J]. Proceedings of the IEEE Circuits, Devices and Systems, 2005, 152(5): 417-424.

GRASSO A D, PALUMBO G, PENNISI S. Comparison of the frequency compensation techniques for CMOS two-stage miller OTAs [J]. IEEE Transactions on Circuits and Systems: II Express Briefs, 2008, 55(11): 1099-1103.

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

A Structure-Semantics-Residual Collaborative Image Compression Framework：Towards Privacy Protection and High-Fidelity Reconstruction

Study on the Thermodynamic Properties in the Anomalous Region of Supercritical Water

Mechanism and Optimal Control Strategy for Hysteresis in Rapid Dehumidification Response of Indirect Thermal Systems in Electric Vehicles

Bi-Level Multi-Obj ective Optimization of a Wind-Solar Coupled Hydrogen Production System Based on the Synergy of Hybrid Electrolyzer Arrays

Numerical Simulation of the Energy Conversion Process in Thermoacoustic Engines with Different Stack Materials

Related Author

No data

Related Institution

No data

⁰