Low Power and Least Significant Bit-First Successive-Approximation Analog-to-Digital Converter for Implantable Medical Devices

doi:10.7652/xjtuxb202003002

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Low Power and Least Significant Bit-First Successive-Approximation Analog-to-Digital Converter for Implantable Medical Devices

更新时间：2025-07-09

- Low Power and Least Significant Bit-First Successive-Approximation Analog-to-Digital Converter for Implantable Medical Devices
- Vol. 54, Issue 3, Pages: 12-19(2020)
- 作者机构：
  
  西安交通大学微电子学院,西安,710049
- 作者简介：
- 基金信息：
- DOI：10.7652/xjtuxb202003002
  CLC： TN432
- Online First：10 March 2020，
  
  Published：2020
- 稿件说明：
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Low Power and Least Significant Bit-First Successive-Approximation Analog-to-Digital Converter for Implantable Medical Devices[J]. 2020, 54(3): 12-19.
DOI：

Low Power and Least Significant Bit-First Successive-Approximation Analog-to-Digital Converter for Implantable Medical Devices[J]. 2020, 54(3): 12-19. DOI： 10.7652/xjtuxb202003002.

摘要

针对植入式医疗设备中关键模块模数转换器(ADC)的超低功耗设计问题

以低功耗的逐次逼近型ADC为基础

提出了低位逐次逼近量化逻辑的模数转换器。量化逻辑主要用于以心电信号为代表的低活动度生物信号

在采用固定分辨率和采样率的情况下

根据信号的变化幅度调整量化次数

以达到降低功耗和压缩数据量的目的

在信号处于基线或缓变间期最少只需要3次量化就可以得到ADC转换结果。采用Global Foundry 0.18 m标准CMOS工艺对该ADC进行了电路和版图设计

仿真结果显示

在1.8 V的电源电压和1 kHz的采样率下

ADC的有效位为9.6 b

核心电路平均电流功耗为64～131 nA。该低位逐次逼近模数转换器特别适合应用于植入或可穿戴医疗设备中低活动度生物信号的模数转换

在保证量化精度的同时显著降低了ADC的功耗。

Abstract

Aiming at the ultra-low power consumption design of the indispensable analog-to-digital converter(ADC)in implantable medical devices

based on the low-power-consumption successive-approximation SAR ADC

a least significant bit(LSB)-first SAR ADC is presented. The LSB-first quantitative logic is mainly used for biological signals of low mobility

such as electrocardiosignal. Under the condition of fixed resolution and sampling rate

the number of quanti-ation is adjusted according to the amplitude of the varying signal

so as to achieve the purpose of reducing power consumption and compressing data amount. Only a minimum number of three quanti-ations is required to obtain a quantitative result when the signal in on the baseline or varies slowly. Global Foundry 0.18--m standard CMOS process is used to design the circuit and layout of the ADC. The post-simulation results show that at the power supply voltage of 1.8 V and the sampling rate of 1 kH-

the effective bits are 9.6 bits

and th

关键词

Keywords

references

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