Implementation of Steady-State Visual Evoked Potential BCI System Based on Field Programmable Gate Array[J]. 2020, 54(2): 158-165.
DOI:
Implementation of Steady-State Visual Evoked Potential BCI System Based on Field Programmable Gate Array[J]. 2020, 54(2): 158-165.DOI: 10.7652/xjtuxb202002020.
Implementation of Steady-State Visual Evoked Potential BCI System Based on Field Programmable Gate Array
To solve the problem that the steady-state visual evoked potential(SSVEP)brain-computer interface(BCI)system requires high computer performance
a SSVEP BCI system based on field programmable gate array(FPGA)and commercial electroencephalogram(EEG)acquisition device is designed by an independent display module based on FPGA. This system reali-es the control of video graphics array(VGA)interface. The paradigm patterns corresponding to different flicker frequencies are allocated according to the displaying refresh frames
and the stable display of the paradigm required to induce SSVEP signals can be achieved. Collecting and analy-ing the flicker outputs of the designed VGA visual stimulator
the presenting frequencies from the visual stimulator are approximately equal to the required frequencies and can be used for SSVEP BCI experiments. Combined with the designed visual stimulator
the FPGA based EEG signal processing and feature recognition are also implemented in this approach. EEG si
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