An improved separated consecutive operand caching algorithm is proposed to focus on the problem that frequent memory-access operations affect the efficiency of Montgomery modular multiplication on embedded processors. The algorithm carefully applies the general idea of consecutive operand caching and optimization to two calculation parts-multiplication and reduction. It separates the whole calculation into many blocks and loads operand in each block only once. The separately integrated mode is used between multiplication and reduction to keep the consecutiveness of operands. The number of memory-access operations on embedded processor is significantly reduced by dynamically using registers and efficient caching of operands. Experiments on processor with MIPS64 structure show that when the modulus is 1 024 bits
the proposed algorithm outperforms the coarsely integrated operand scanning algorithm by a factor of 4.17%. The proposed algorithm can be used for public-key cryptography to improve the efficiency of both the modular multiplication and the public-key algorithms.
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