A dynamic mapping algorithm(DMA)for network-on-chip(NoC)based on cluster is proposed to solve the problems that the traditional one-to-one mapping relationship causes low utilization ratio of resource nodes and high communication power. Firstly
connected task nodes with high traffic load are clustered using a branch-and-bound approach to reduce the total communication volume of task graphs. Then an adaptive particle swarm algorithm is used to obtain the optimal mapping results. Finally
the dynamic migration strategy is used to cluster the task nodes that occupy an individual resource node in the optimal mapping results. Experimental results and comparisons with the random mapping
the dynamic spiral mapping algorithm(DSMA)and the nearest neighbor(NN)algorithm show that the proposed algorithm respectively reduces the communication power of the task graph by about 73.93%
46.37% and 14.55%
and the occupancy rate of the NoC area by about 50%
50% and 33.3%.
关键词
Keywords
references
BENINI L, MICHELI G D. Networks on chips: a new SoC paradigm [J]. IEEE Transactions on Computer, 2002, 35(1): 70-78.
KUMAR S, JANTSCH A, SOININEN J P, et al. A network on chip architecture and design methodology [C]∥Proceedings of IEEE Computer Society Annual Symposium on VLSI. Los Alamitos, CA, USA: IEEE Computer Society, 2002: 117-124.
BJERREGAARD T, MAHADEVAN S. A survey of research and practices of network-on-chip [J]. ACM Computing Surveys, 2006, 38(1): 1-51.
YANG Shengguang, LI Li, GAO Minglun, et al. An energy- and delay-aware mapping method of NoC [J]. Acta Electronica Sinica, 2008, 36(5): 937-942.
白海. 片上网络映射算法研究和设计 [D]. 成都: 电子科技大学, 2009.
MAQSOOD T, ALI S, MALIK S U R, et al. Dynamic task mapping for network-on-chip based systems [J]. Journal of Systems Architecture, 2015, 61(7): 293-306.
YANG Pengfei, WANG Quan. An effective scheduling and mapping algorithm of tasks for heterogeneous NoC based MPSoC [J]. Journal of Xi'an Jiaotong University, 2015, 49(6): 72-76.
MEHRAN A, KHADEMZADEH A, SAEIDI S. DSM: a heuristic dynamic spiral mapping algorithm for network on chip [J]. IEICE Electronics Express, 2008, 5(13): 464-471.
CARVALHO E, CALAZANS N, MORAES F. Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs [C]∥Proceedings of 18th IEEE/IFIP International Workshop on Rapid System Prototyping. Piscataway, NJ, SUA: IEEE, 2007: 34-40.
SINGH A K, SRIKANTHAN T, KUMAR A, et al. Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms [J]. Journal of Systems Architecture, 2010, 56(7): 242-255.
FALAHATI H, KOOHI S, HESSABI S. Application-based dynamic reconfiguration in optical network-on-chip [J]. Computers Electrical Engineering, 2015, 45: 417-429.
CARVALHO E, CALAZANS N, MORAES F. Dynamic task mapping for MPSoCs [J]. IEEE Design and Test of Computers, 2010, 27(5): 26-35.
YE T T, MICHELI G D, BENINI L. Analysis of power consumption on switch fabrics in network routers [C]∥Proceedings of the 39th Annual Design Automation Conference. Piscataway, NJ, USA: IEEE, 2002: 524-529.
HU J, MARCULESCU R. Energy- and performance-aware mapping for regular NoC architectures [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, 24(4): 551-562.
BETHART R, KENNEDY J. A new optimizer using particle swarm theory [C]∥Proceeding of the 6th International Symposium on Micro Machine and Human Science. Piscataway, NJ, USA: IEEE, 1995: 39-43.