A low time complexity method for checking the correctness of ARM memory model is proposed by identifying the pending windows of microprocessor and introducing the restrictions of time order
and a validation tool is presented. The ARM memory model is explored and the formal definition of the model is given in the method. The time order constraints are obtained by scanning the performance counters of the ARM memory system periodically. The validation tool consists of three parts
namely
a random instruction generation module
a performance counter recording module and a results analysis module. The tool can effectively handle millions of lines of ARM multicore program because of the low time complexity of the algorithm. The validation tool is written in C++
and the length of the access memory instructions can be adjusted dynamically in run-time
which supports high extendability. Experiments with several infected errors in an ARM MPCore simulator show that the validation tool can detect these errors correctly
and that the proposed validation method and tool can effectively verify the ARM memory model.
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references
ARM. ARM architectural reference manual [M]. Cambridge, UK: ARM, 2008.
COLLIER W W. Reasoning about parallel architectures [M]. Upper Saddle River, NJ, USA: Prentice-Hall, 1992.
Intel Corporation. Intel 64 architecture memory ordering white paper [R]. San Francisco, CA, USA: Intel Corporation, 2007.
HANGAL S, VAHIA D, MANOVIT C, et al. TSOtool: a program for verifying memory systems using the memory consistency model [J]. SIGARCH Computer Architecture News, 2004, 32(2): 114-123.
MANOVIT C, HANGAL S. Efficient algorithms for verifying memory consistency [C]∥Proceedings of the 17th Annual ACM Symposium on Parallelism in Algorithms and Architectures. New York, USA: ACM Press, 2005: 245-252.
ROY A, ZEISSET S, FLECKENSTEIN C, et al. Fast and generalized polynomial time memory consistency verification [C]∥Proceedings of the International Conference on Computer Aided Verification. Berlin, Germany: Springer, 2006: 503-516.
MANOVIT C, HANGAL S. Completely verifying memory consistency of test program executions [C]∥Proceedings of the 12th International Symposium on High-Performance Computer Architecture. Washington DC, USA: IEEE Computer Society Press, 2006: 166-175.
CHEN Yunji, LV Yi, HU Weiwu, et al. Fast complete memory consistency verification [C]∥Proceedings of the 15th International Symposium on High-Performance Computer Architecture. Washington DC, USA: IEEE Computer Society Press, 2009: 381-392.
WANG Pengyu, CHEN Yunji, SHEN Haihua, et al. Memory consistency verification of chip multi-processor [J]. Journal of Software, 2010, 21(4): 863-874.
LV Zheng, CHEN Hao, CHEN Feng, et al. Fast verification of memory consistency for chip multi-processor [C]∥Proceedings of the Seventh International Conference on Computational Intelligence and Security. Washington DC, USA: IEEE Computer Society, 2011: 1497-1502.
LV Zheng, CHEN Hao, CHEN Feng, et al. MOTEC: a tool for quick verification of memory consistency model [J]. Computer Engineering, 2012, 38(11): 242-246.