Research and Design of 12 bit 100 MHz Pipelined Analog-to-Digital Converter

王小力 1; 刘云涛 2

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Research and Design of 12 bit 100 MHz Pipelined Analog-to-Digital Converter

更新时间：2025-12-08

- Research and Design of 12 bit 100 MHz Pipelined Analog-to-Digital Converter
- Vol. 42, Issue 10, Pages: 1204-1208(2008)
- 作者机构：
  
  西安交通大学超大规模集成电路设计研究中心,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP335
- Online First：10 October 2008，
  
  Published：2008
- 稿件说明：
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王小力 1, 刘云涛 2. Research and Design of 12 bit 100 MHz Pipelined Analog-to-Digital Converter[J]. 2008, 42(10): 1204-1208.
DOI：

王小力 1, 刘云涛 2. Research and Design of 12 bit 100 MHz Pipelined Analog-to-Digital Converter[J]. 2008, 42(10): 1204-1208. DOI：

摘要

为了解决流水线结构模数转换器(ADC)的高速度、高精度和大动态范围兼顾问题

提出了一种改进的2.5 b/级与1.5 b/级结构相结合的系统设计方案.该系统中

流水线第1级采用2.5 b/级结构

2～10级均采用1.5 b/级结构

改进后的结构增大了系统的动态范围

同时更加模块化

降低了电路设计的复杂度.设计了2级Bicmos运算放大器

并提出了一种全新的应用于1.5 b/级结构的差分比较器.所设计的运算放大器可同时实现高增益、大带宽

电路速度快

不需要额外的补偿电容

可应用于高频环境

并具有较大的输出摆幅.所设计的差分比较器电路简化

节省了元件

不需电阻分压网络产生参考电压

减小了芯片面积.ADC系统采用0.35 μm Bicmos工艺技术和3.3 V工作电压

经仿真实验

在100 MHz的采样频率下

该系统的信噪比为73.7 dB

对应的有效位为11.95 b

无杂散动态范围为87.4 dB

实现了12位高分辨率和100 MHz的高采样速度.

Abstract

An improved architecture of combining 2.5 b/stage and 1.5 b/stage structures is presented to solve the problem that high speed

high precision and dynamic specification are concerned at the same time in pipelined analog-to-digital converters(ADC). In the system

2.5 b/stage structure is applied in the first stage

and 1.5 b/stage structures are applied in 2 to 10 stages

which extends the dynamic range of the system

modularizes the design and decreases the complexity of circuits. Two-stage Bicmos operational amplifier and a novel differential comparator that is used in 1.5 b/stages are designed. The operational amplifier can achieve high gain

bandwidth

fast speed

output swing at the same time

does not need compensation capacitance

and could operate in high frequency environment. The comparator does not need resistances to produce reference voltage

decreases the number of devices and saves chip area. The ADC is designed with 0.35 μm Bicmos process and 3.3 V power supply. The simulation results show that the SNR of system is 73.7 dB

the effective number of bits is 11.95 b

and spurious free dynamic range is 87.4 dB in 100 MHz sampling rate environment. The ADC can achieve 12 b converter precision when the sampling rate is 100 MHz.

关键词

Keywords

references

RAZAVI B. Principle of data conversion system design [M]. New York, USA:Wiley-IEEE Press, 1995.

GRAY P R, HURST P J. Analysis and design of analog integrated circuits [M]. 4th ed. New York, USA: John Wiley Sons, 2000.

LEWIS S H, FETTERMAN S, GROSS G F, et al. A 10-b20-Msample/s analog-to-digital converter[J]. IEEE Journal of Solid-State Circuits,1992, 27(3):351-356.

GUTMANN S D, ROSE K R J. A 87 dB 2.3 GHz SiGe BiCMOS operational transconductance amplifier [C]∥ Proceedings of the 2004 International Symposium on Circuits and Systems.Piscataway, NJ, USA:IEEE, 2004: 677-680.

Devarajan S. Design of BiCMOS operational amplifiers for switched capacitor applications [D]. New York,USA: Rensselaer Polytechnic Institute, 2003.

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