Analog Filter Design with Low Noise for Digital Video Broadcasting-Handheld Tuner

戚建烨 1; 王小力 1; 王守军 2

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Analog Filter Design with Low Noise for Digital Video Broadcasting-Handheld Tuner

更新时间：2025-12-08

- Analog Filter Design with Low Noise for Digital Video Broadcasting-Handheld Tuner
- Vol. 43, Issue 2, Pages: 72-76(2009)
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN47
- Online First：10 February 2009，
  
  Published：2009
- 稿件说明：
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戚建烨 1, 王小力 1, 王守军 2. Analog Filter Design with Low Noise for Digital Video Broadcasting-Handheld Tuner[J]. 2009, 43(2): 72-76.
DOI：

戚建烨 1, 王小力 1, 王守军 2. Analog Filter Design with Low Noise for Digital Video Broadcasting-Handheld Tuner[J]. 2009, 43(2): 72-76. DOI：

摘要

为了降低零中频移动数字电视调谐器中模拟滤波器的噪声

提出了一种新的基于低噪声运算放大器设计的技术.该技术通过对运放共模回馈小信号等效电路的分析

采用左半平面零点对电路进行稳定性补偿

在保证相位裕度的前提下优化晶体管尺寸

降低低频闪烁噪声.仿真结果表明

同优化前相比

该运放在1 kHz处的噪声系数降低约3.4 dB.应用该技术设计了一个8阶切比雪夫II型低通滤波器

该滤波器具有2.85 MHz、3.33 MHz、3.8 MHz 3种可编程带宽模式

在偏离带宽1.4 MHz处实现了45 dB衰减.芯片采用台积电0.18 μm 混合信号1P 6M CMOS工艺设计

面积为2.4 mm×0.72 mm.对电路进行了带版图寄生的后仿真

结果表明滤波器的噪声性能满足系统设计要求.

Abstract

To reduce the noise of the analog filter in zero intermediate-frequency digital video broadcasting-handheld tuner

a new design technique base on low noise operational-amplifier(Op-amp)is presented. The small signal model of Op-amp's common mode feedback circuit is quantitatively analyzed

and then a left-half plane zero is leaded into the common mode feedback loop to compensate the stability. The size of the transistor is optimized to reduce the flicker noise under a determinate phase margin. Simulation results show that the noise figure of Op-amp at 1 kHz frequency is decreased by 3.4 dB

compared with the unimproved technique. The proposed technique is used in an eighth order Chebyshev II low pass filter that has three programmable bandwidths: 2.85 MHz

3.33 MHz

and 3.8 MHz

and the attenuation is 45 dB at offset of 1.4 MHz. The filter is implemented in Taiwan semiconductor manufacturing corporation 0.18 μm mixed-signal 1P 6M CMOS process

which occupies a chip area of 2.4 mm×0.72 mm. The post-layout simulation results show that the noise performance satisfies the design requirement of the system.

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references

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