Implementation of Joint Servo Controller on-Chip

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Implementation of Joint Servo Controller on-Chip

更新时间：2025-07-09

- Implementation of Joint Servo Controller on-Chip
- Vol. 44, Issue 7, Pages: 70-74(2010)
- 作者机构：
  
  1. 哈尔滨工业大学机器人技术与系统国家重点实验室,哈尔滨,150080
  2. 哈尔滨工业大学电气工程博士后流动站,哈尔滨,150080
- 作者简介：
- 基金信息：
- DOI：
  CLC： TP242.6
- Online First：10 July 2010，
  
  Published：2010
- 稿件说明：
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Implementation of Joint Servo Controller on-Chip[J]. 2010, 44(7): 70-74.
DOI：

Implementation of Joint Servo Controller on-Chip[J]. 2010, 44(7): 70-74. DOI：

摘要

提出了一种关节片上位置伺服系统控制器的设计方案

并在一片可编程逻辑器件(FPGA)中得到了具体验证和实现.该方案利用FPGA的硬件逻辑单元实现了关节内部所有传感器信息的采集、M/T法测速、电机的脉宽调制和矢量控制

并在FPGA内嵌入了NIOS II软核处理器和控制器局域网CAN总线控制器

实现了关节空间的轨迹规划、位置控制以及与主控计算机的CAN总线通讯.通过SOPC Builder工具实现了硬件逻辑单元和软核控制器的集成.实验结果表明

设计的关节片上位置伺服系统可有效地提高关节控制器系统的集成度

从而减小了电路板的尺寸

增强了系统的抗干扰能力和关节控制性能.

Abstract

A design of joint position servo system controller on-chip is proposed

and a specific verification and implementation are achieved by one field programmable gate array(FPGA). All sensor information collection within the joints

speed detection with M/T method

motor PWM and vector control algorithm are obtained with FPGA hardware logic cells. The joint space trajectory planning

position control

and CAN bus communication with the host computer are obtained with the NIOS II soft-core processor and CAN bus controller

which are embedded in FPGA. The system integration of the logic cell and soft-core processor is achieved by the SOPC Builder tools. Experimental results show that the joint control system integration is improved

the size of the circuit board is reduced

and the anti-jamming capability and joint control performance are enhanced due to the design of the joint position servo system on-chip.

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references

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