A Digital Calibration Technique of Pipelined Analog-to-Digital Converter

贾华宇; 陈贵灿; 程军; 张鸿; 沈磊

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A Digital Calibration Technique of Pipelined Analog-to-Digital Converter

更新时间：2025-12-08

- A Digital Calibration Technique of Pipelined Analog-to-Digital Converter
- Vol. 42, Issue 8, Pages: 991-995(2008)
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN432
- Online First：10 August 2008，
  
  Published：2008
- 稿件说明：
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贾华宇, 陈贵灿, 程军, et al. A Digital Calibration Technique of Pipelined Analog-to-Digital Converter[J]. 2008, 42(8): 991-995.
DOI：

贾华宇, 陈贵灿, 程军, et al. A Digital Calibration Technique of Pipelined Analog-to-Digital Converter[J]. 2008, 42(8): 991-995. DOI：

摘要

为了降低流水线模数转换器中数字校准电路的规模和功耗

提出了一种新的基于信号统计规律的后台数字校准技术.该技术采用自适应搜索算法和二元单调函数的幅值增量比较算法

分别对基于信号统计规律的数字校准技术中的距离估计电路和查找表进行优化设计

减少了距离估计所需的数字电路和查找表所需的ROM空间

极大地降低了数字电路的规模和功耗.应用该校准技术实现了一个12 位、采样率为4×10

-1

的流水线模数转换器.测试结果表明

同优化前相比

该芯片数字电路的功耗降低了93%

所需ROM空间减小了95%.整个芯片采用SMIC 0.18 μm CMOS工艺设计

总功耗为210 mW

芯片面积为3.3 mm×3.7 mm.

Abstract

To reduce the power dissipation and chip size of digital calibration circuits of pipelined analog-to-digital converter(ADC)

a new statistics-based background calibration technique is presented. In order to improve both the residual distance estimator circuit and the design of look up table(LUT)in binary monotonically function

an adaptive search algorithm and a magnitude incremental comparison algorithm are used in the calibration technique. The technique can reduce the digital circuits' scale of distance estimator and the memory of ROM of LUT. By using the technique

the power dissipation in digital circuits and the chip size are reduced significantly. The improved technique is applied in the implementation of one 12 bit 4×10

-1

pipelined ADC. The

tested results show that power consumption of digital circuits is reduced by 93% and the memory of ROM is saved by 95%

compared with the unimproved technique. The ADC implemented in SMIC 0.18 μm CMOS process consumes 210 mW

and occupies a chip area of 3.3 mm×3.7 mm.

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references

GULATI K, LEE H S. A low-power reconfigurable analog-to-digital converter [J]. IEEE Journal of Solid-State Circuits, 2001, 36(12): 1900-1911.

KIM H C, JEONG D K, KIM W. A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters [J]. IEEE Transactions on Circuits and Systems, 2006, 53(4): 795-801.

MURMANN B, BOSER B E. Digitally assisted pipelined ADCs [M].Boston, MA, USA: Kluwer Academic Publishers, 2004:75-107.

MURMANN B, BOSER B E. A 12b 75 MS/s pipelined ADC using open-loop residue amplification [J]. IEEE Int Solid-State Circuits Conf Dig Tech Papers, 2003, 38(12): 2040-2050.

IROAGA E, MURMANN B. A 12-Bit 75-MS/s pipelined ADC using incomplete settling [J]. IEEE Journal of Solid-State Circuits, 2007, 42(4): 748-756.

LI J, MOON U N. Background calibration techniques for multistage pipelined ADCs with digital redundancy [J]. IEEE Transactions on Circuits and Systems, 2003, 50(9): 531-538.

MING J, LEWIS S H, An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration [J]. IEEE Journal of Solid-State Circuits, 2001, 36(10): 1489-1497.

沈磊,陈贵灿,谷宁静. 一种基于LUT的二元单调函数的幅值增量比较算法[J]. 微电子学与计算机, 2006, 23(7): 141-143.

SHEN Lei, CHEN Guican, GU Ningjing. Magnitude incremental comparison for a binary monotone function based on LUT [J]. Microelectronics Computer, 2006, 23(7): 141-143.

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