Low Power and High Speed Open-Loop Residue Amplifier for Pipelined Analog-to-Digital Converters

张鸿; 陈贵灿; 程军; 贾华宇

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Low Power and High Speed Open-Loop Residue Amplifier for Pipelined Analog-to-Digital Converters

更新时间：2025-12-08

- Low Power and High Speed Open-Loop Residue Amplifier for Pipelined Analog-to-Digital Converters
- Vol. 42, Issue 6, Pages: 751-755(2008)
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN432
- Online First：09 June 2008，
  
  Published：2008
- 稿件说明：
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张鸿, 陈贵灿, 程军, et al. Low Power and High Speed Open-Loop Residue Amplifier for Pipelined Analog-to-Digital Converters[J]. 2008, 42(6): 751-755.
DOI：

张鸿, 陈贵灿, 程军, et al. Low Power and High Speed Open-Loop Residue Amplifier for Pipelined Analog-to-Digital Converters[J]. 2008, 42(6): 751-755. DOI：

摘要

为了降低流水线模数转换器(ADC)中余量放大器的功耗并提高其速度

提出了一种新的开环余量放大器结构及其增益控制方法. 该放大器采用简单差动对结构

并使用放大器的复制电路和一个差动差值放大器来控制主放大器输入对管的跨导

以稳定开环余量放大器的增益. 所提出的放大器结构可以工作在低电源电压下

而且不需要共模反馈电路

与采用共源共栅结构和共模反馈的开环放大器相比

功耗更低

响应速度更快. 仿真结果表明

所提开环余量放大器的功耗仅为5.5 mW

在满幅度阶跃输入的情况下

输出建立时间小于3 ns.将该开环余量放大器应用到采用数字校准的流水线ADC中

实现了采样率为4×10

-1

的12位模数转换.

Abstract

To reduce the power consumed by the residue amplifier in pipelined analog-to-digital converter(ADC)and enhance its speed

a new topology of the open-loop residue amplifier and its gain control circuit were presented. The open-loop residue amplifier adopts a simple differential architecture. In order to stabilize the gain of the amplifier

a replica amplifier and a differential difference amplifier are used to control the transconductance of the amplifier's input transistors. The proposed open-loop residue amplifier can be used in applications of lower supply voltage. Common-mode control circuits are not needed for the amplifier because the gain control circuit has no influence on the output common-mode level of the amplifier. The proposed amplifier a

chieves the designs of lower power consumption and higher response speed compared with the amplifier that adopts cascode and common-mode feedback architecture. Designed in a 0.18 μm CMOS technology

the open-loop amplifier consumed only 5.5 mW at a 1.8 V supply voltage. The settling time of the open-loop residue amplifier is less than 3 ns at maximum step input. A pipelined ADC using this open-loop residue amplifier achieves a resolution of 12 bit and a sampling rate of 4×10

-1

by carrying out digital calibration in background.

关键词

Keywords

references

IROAGA E, MURMANN B. A 12-Bit 75-MS/s pipelined ADC using incomplete settling [J]. IEEE J Solid-State Circuits, 2007, 42(4): 748-756.

SHEN D L, LEE T C. A 6-bit 800-MS/s pipelined A/D converter with open-loop amplifiers [J]. IEEE J Solid-State Circuits, 2007, 42(2): 258-268.

MURMANN B, BOSER B E. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification [J]. IEEE J Solid-State Circuits, 2003, 38(12): 2040-2050.

TAVASSOLI B, SHOAEI O. Digital background calibration of pipeline ADC with open-loop gain stage [C]∥Proceedings of 2006 IEEE International Symposium on Circuits and Systems. Piscataway,NJ, USA: IEEE, 2006: 5255-5258.

YANG W, KELLY D, MEHR I,et al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input [J]. IEEE J Solid-State Circuits, 2001, 36(12): 1931-1936.

MURMANN B, BOSER B E. Digitally assisted pipeline ADCs [M]. Boston, MA,USA: Kluwer Academic, 2004: 71-72.

ALZAHER H, ISMAIL M. A CMOS fully balanced differential difference amplifier and its applications [J]. IEEE Trans on Circuits and Systems:II, Analog and Digital Signal Processing, 2001, 48(6): 614-620.

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