An Easy Linear-Compression Test Pattern Generation Method

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An Easy Linear-Compression Test Pattern Generation Method

更新时间：2025-07-09

- An Easy Linear-Compression Test Pattern Generation Method
- Vol. 44, Issue 12, Pages: 76-81(2010)
- 作者机构：
  
  西安交通大学电子与信息工程学院,西安,710049
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN407;TP391.7
- Online First：10 December 2010，
  
  Published：2010
- 稿件说明：
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An Easy Linear-Compression Test Pattern Generation Method[J]. 2010, 44(12): 76-81.
DOI：

An Easy Linear-Compression Test Pattern Generation Method[J]. 2010, 44(12): 76-81. DOI：

摘要

为解决VLSI测试中数据量大、功耗高和故障检测难等问题

提出一种易于线性压缩的测试图形生成方法(LCG法).与传统方法不同

LCG法先解析出一类每个向量内部具有线性关系的测试序列

这种线性关系是基于单输入变化序列的

构成的测试序列可有效地减少被测电路内部的开关活动.测试生成时只需搜索测试向量少量的位值

其他位的值按预定义的线性关系解析出

再通过故障模拟的方法确认测试图形.压缩后的测试图形为其少量位的内容

具有压缩率高、易于实现、功耗低和覆盖率高的特点.对ISCAS89中5个最大的基准电路的实验结果表明

LCG法在固定故障覆盖率大于96%的情况下

压缩率都在10倍以上

甚至可以达到100倍以上.

Abstract

An easy linear-compression test pattern generation method(LCG)is proposed to solve the problems of data volume

power and fault detection in VLSI test. Unlike traditional test generation methods

LCG method extracts a class of test sequences with linear relationships existing in each vector. The linear relationships are based on single input change sequences

and the resulting test sequence can effectively reduce switching activities in a CUT(circuit under test). During test pattern generation

LCG method finds values only for a small portion of the bits of a test vector

and values for other bits of the test vector are assigned according to the predefined linear relationships. Test patterns are justified by fault simulations. The compressed test pattern consists of the small portion of the bits of the original pattern. Therefore

the proposed LCG method has features of high compression ratio

easy implementation

low power and high fault coverage. Experimental results on the five largest ISCAS89 benchmarks show that the LCG method achieves stuck-at fault coverage more than 96%

and test compression ratios over 10 times for all benchmarks

and even 100 times for some benchmarks.

关键词

Keywords

references

KATTI R S, RUAN Xiaoyu, KHATTRI H. Multiple-output low-power linear feedback shift register design [J]. IEEE Transactions on Circuits and Systems: I, 2006, 53(7):1487-1495.

WANG Laung-Terng, WEN Xiaoqing, WU Shianling, et al. VirtualScan: test compression technology using combinational logic and one-pass ATPG [J]. IEEE Design Test of Computers, 2008, 25(2):122-130.

MOORE B, MANGRUM M, SELLATHAMBY C, et al. Non-contact testing for SoC and RCP(SIPs)at advanced nodes[C]∥Proceedings of International Test Conference 2008. Piscataway, NJ, USA: IEEE, 2008:1-10.

MAHAMMAD S N, VEEZHINATHAN K. Constructing online testable circuits using reversible logic[J]. IEEE Transactions on Instrumentation and Measurement, 2010,59(1): 101-109.

NOURANI M, TEHRANIPOOR M, AHMED N. Low-transition test pattern generation for BIST-based applications [J]. IEEE Transactions on Computers, 2008,(3)57:303-315.

WANG Seongmoon, GUPTA S K. DS-LFSR: a new BIST TPG for low heat dissipation [J]. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2002, 21(7):842-851.

EL-MALEH A, OSAISA Y. Test vector decomposition-based static compaction algorithms for combinational circuits [J]. ACM Transactions on Design Automation of Electronic Systems, 2003, 8(4):430-459.

AYARI B, KAMINSKA B. A new dynamic test vector compaction for automatic test pattern generation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994, 13(3):353-358.

CHEN Zhen, SETH S, XIANG Dong, et al. A unified solution to scan test volume, time, and power minimization[C]∥Proceedings of 23rd International Conference on VLSI Design. Piscataway, NJ, USA: IEEE, 2010:9-14.

STELIOS N N, MARIA K M. Test set generation with a large number of unspecified bits using static and dynamic techniques [J]. IEEE Transactions on Computers, 2010, 59(3):301-316.

LI Lei, CHAKRABARTY K. Test set embedding for deterministic BIST using a reconfigurable interconnection network [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23(9): 1289-1305.

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