A Nanowatt Tracking-Quantizing Successive Approximation Register Analog-to-Digital Converter for Sparse Signal Acquisition

ZHENG Congyu; WANG Yuyuan; SUN Aoran; HAO Yun; XU Jiangtao; ZHANG Jie; WANG Ruitao; ZHANG Hong

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A Nanowatt Tracking-Quantizing Successive Approximation Register Analog-to-Digital Converter for Sparse Signal Acquisition

更新时间：2026-09-02

- A Nanowatt Tracking-Quantizing Successive Approximation Register Analog-to-Digital Converter for Sparse Signal Acquisition
- JOURNAL OF XI’AN JIAOTONG UNIVERSITY (2026)
- 作者机构：
  
  西安交通大学微电子学院，710049，西安
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN432
- Received：04 June 2026，
  
  Revised：2026-08-04，
  
  Accepted：05 August 2026，
- 稿件说明：
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ZHENG Congyu, WANG Yuyuan, SUN Aoran, et al. A Nanowatt Tracking-Quantizing Successive Approximation Register Analog-to-Digital Converter for Sparse Signal Acquisition[J]. JOURNAL OF XI’AN JIAOTONG UNIVERSITY,2026.
DOI：

ZHENG Congyu, WANG Yuyuan, SUN Aoran, et al. A Nanowatt Tracking-Quantizing Successive Approximation Register Analog-to-Digital Converter for Sparse Signal Acquisition[J]. JOURNAL OF XI’AN JIAOTONG UNIVERSITY,2026. DOI：

摘要

针对低频稀疏信号采集传感器中模数转换器（ADC）以固定速率采样导致的数据冗余和能量浪费的问题，提出了一种跟踪-量化型10 bit逐次逼近模数转换器（SAR-ADC）。该SAR-ADC由跟踪、启动和量化三部分组成：跟踪部分通过电容型数模转换器（CDAC）以近零功耗跟踪输入信号；启动部分采用脉冲转换器将传感器系统产生的触发脉冲转换为异步控制信号，从而控制CDAC完成采样并启动量化过程；量化部分由CDAC、比较器、基准缓冲器和逻辑电路一同完成10 bit逐次逼近量化，量化完成后SAR-ADC返回跟踪状态。该SAR-ADC支持传感器系统在时间域上实现变速率采样策略并显著减少硬件开销。此外，在逻辑电路中设计低漏电长延时产生电路，有效降低了延时单元的功耗。采用180 nm CMOS工艺对提出的SAR-ADC进行设计并通过流片测试验证。实测结果表明：在2 V供电电压和10

/s采样率下，该SAR-ADC的有效位数为9.57 bit，满足心电信号采集所需的精度要求；在自适应双频采样下（10

/s 和10

/s），该SAR-ADC的功耗仅为固定速率采样ADC的16.7%。该SAR-ADC可应用在生物医疗传感器中实现对稀疏信号的低功耗采集。

Abstract

To address the problems of data redundancy and energy waste caused by fixed-rate sampling of analog-to-digital converters (ADCs) in low-frequency sparse signal acquisition sensors

a 10-bit tracking-quantizing successive approximation register ADC (SAR-ADC) is proposed. The proposed SAR-ADC consists of three functional modules: tracking module

startup module

and quantization module. The tracking module tracks the input signal via a capacitive digital-to-analog converter (CDAC) with near-zero power consumption. In the startup module

a pulse converter converts the trigger pulse generated by the sensor system into asynchronous control signals

which control the CDAC to complete sampling and initiate the quantization process. In the quantization module

10-bit successive approximation quantization is jointly accomplished by the CDAC

comparator

reference buffer and logic circuit; upon completion of quantization

the SAR-ADC returns to the tracking state. The SAR-ADC enables sensor systems to implement a time-domain variable-rate sampling strategy and significantly reduces hardware overhead. In addition

a low-leakage long-delay generation circuit is designed in the logic circuit

which effectively reduces the power consumption of the delay unit. The proposed SAR-ADC was designed in a 180-nm CMOS process and validated through tape-out testing. Measurement results demonstrate that under a 2-V supply voltage and a sampling rate of 10³ /s

the proposed SAR-ADC achieves an effective number of bits (ENOB) of 9.57 bits

which satisfies the accuracy requirement for ECG signal acquisition. Under adaptive dual-rate sampling (10³ /s and 10² /s)

the power consumption of the proposed SAR-ADC is only 16.7% of that of a fixed-rate sampling ADC. The proposed SAR-ADC can be applied in biomedical sensors to realize low-power acquisition of sparse signals.

关键词

Keywords

references

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