[1]邹家轩,于宗光,魏敬和,等.面向空间辐照环境的星载高速数字接口芯片设计方法[J].西安交通大学学报,2020,54(06):058-65.[doi:10.7652/xjtuxb202006008]
 ZOU Jiaxuan,YU Zongguang,WEI Jinghe,et al.A Design Approach of Satellite High-Speed Digital Interface Chips for Space Radiation Environment[J].Journal of Xi'an Jiaotong University,2020,54(06):058-65.[doi:10.7652/xjtuxb202006008]
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面向空间辐照环境的星载高速数字接口芯片设计方法
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《西安交通大学学报》[ISSN:0253-987X/CN:61-1069/T]

卷:
54
期数:
2020年第06期
页码:
058-65
栏目:
出版日期:
2020-06-10

文章信息/Info

Title:
A Design Approach of Satellite High-Speed Digital Interface Chips for Space Radiation Environment
文章编号:
0253-987X(2020)06-0058-08
作者:
邹家轩12 于宗光12 魏敬和2 陈珍海2 李鹏伟3
1.西安电子科技大学微电子学院, 710077, 西安; 2.中国电子科技集团公司第五十八研究所, 214035, 江苏无锡; 3.中国宇航元器件工程中心, 100094, 北京
Author(s):
ZOU Jiaxuan12 YU Zongguang12 WEI Jinghe2 CHEN Zhenhai2 LI Pengwei3
1. School of Microelectronics, Xidian University, Xi’an 710077, China; 2. The 58th Research Institute, China Electronic Technology Group Corporation, Wuxi, Jiangsu 214000, China; 3. China Aerospace Components Engineering Center, Beijing 100094, China
关键词:
单粒子辐照 抗辐照加固 高速串行接口 RS编码 8B/10B编码
Keywords:
single-particle radiation radiation hardening high-speed serial interface RS codec 8B/10B codec
分类号:
TN43
DOI:
10.7652/xjtuxb202006008
文献标志码:
A
摘要:
针对空间应用的高速串行接口芯片易受单粒子辐照而出现误码的问题,提出了一种面向空间辐照环境的星载高速数字接口芯片设计方法。首先,针对空间辐照诱发单比特错误导致高速串行接口传输出错问题,计算辐照时的高速串行接口误码率最劣值; 然后,通过误码率最劣值计算出辐照环境下高速串行接口无误码传输所需的增益; 最后,采用叠加编码增益及辐照干扰的高速串行接口链路评价模型,计算出高速串行接口物理编码子层(PCS)中不同编码方式的编码增益,并评估编码增益对辐照降低高速串行接口误码率的补偿效果,根据补偿效果选择RS-8B/10B级联编码作为PCS编码。采用该高速数字接口芯片设计方法设计了一款速率为3.125 Gb/s的抗辐照高速串行接口芯片,其面积为4.84 mm2,典型功耗为207 mW。单粒子辐照试验结果表明,对比传统设计方法,新的设计方法将芯片的单比特错误阈值提升了9 MeV·cm2/mg。
Abstract:
A design approach for high-speed digital interface in satellite under space radiation is proposed to solve the problem that high-speed serial interface chips for space applications are susceptible to single-particle radiation. Firstly, the worst bit error rate(BER)of the high-speed serial interface is calculated over the issue of transmission error resulting in single bit error induced by space radiation. The gain required by zero-bit-error transmission in the radiation environment is deduced based on the worst BER; and then the coding gain for variable coding schemes in physical coding sub-layer(PCS)of the high-speed serial interface is inferred by using the link evaluation model featured with superposed coding gain and radiation interference. Meanwhile, the compensation effect of coding gain to BER degradation induced by radiation is evaluated, RS-8B/10B cascade coding is selected as the PCS coding according to the compensation effect. Finally, a 3.125-Gb/s radiation-hardened high-speed serial interface chip is designed using this design approach, and the chip occupies 4.84 mm2 chip area and consumes 207 mW typical power. Experimental results with single-particle radiation show that the single-bit error radiation threshold for the proposed design approach scheme is 9 MeV·cm2/mg higher than that for the traditional design approach scheme.

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备注/Memo

备注/Memo:
收稿日期: 2019-10-30。作者简介: 邹家轩(1982—),男,博士生; 于宗光(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(61704161); 中央军委装备发展部“十三五”微电子预研基金资助项目(31513010412)。
更新日期/Last Update: 2020-06-10