[1]焦子豪,张瑞智,金锴,等.用于高速模数转换器的非对称全差分参考电压缓冲器[J].西安交通大学学报,2020,54(05):109-116.[doi:10.7652/xjtuxb202005015]
 JIAO Zihao,ZHANG Ruizhi,JIN Kai,et al.Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors[J].Journal of Xi'an Jiaotong University,2020,54(05):109-116.[doi:10.7652/xjtuxb202005015]
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用于高速模数转换器的非对称全差分参考电压缓冲器
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《西安交通大学学报》[ISSN:0253-987X/CN:61-1069/T]

卷:
54
期数:
2020年第05期
页码:
109-116
栏目:
出版日期:
2020-05-10

文章信息/Info

Title:
Asymmetric Fully-Differential Reference Voltage Buffer for High Speed Analog-Digital Convertors
文章编号:
0253-987X(2020)05-0109-08
作者:
焦子豪1 张瑞智1 金锴1 盛炜2 张鸿1
1.西安交通大学微电子学院, 710049, 西安; 2.中国电子科技集团公司第五十八研究所, 214000, 江苏无锡
Author(s):
JIAO Zihao1 ZHANG Ruizhi1 JIN Kai1 SHENG Wei2 ZHANG Hong1
1. School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China; 2. China Electronic Technology Group Corporation No.58 Research Institute, Wuxi, Jiangsu 214000, China
关键词:
高速模数转换器 参考电压缓冲器 AB类放大器 非对称输出
Keywords:
high speed analog-to-digital converter reference voltage buffer class-AB amplifier asymmetric output
分类号:
TN432
DOI:
10.7652/xjtuxb202005015
文献标志码:
A
摘要:
针对现有高速高精度模数转换器(ADC)芯片内部参考电压缓冲器需要牺牲很大功耗来满足精度和速度要求的问题,提出了一种具有非对称AB类输出级的全差分参考电压缓冲器,能够以较低的运放增益满足缓冲器高精度的需求,从而显著降低缓冲器的功耗。通过引入非对称的输出结构,参考电压缓冲器只需要满足高带宽,不再需要较高的开环增益; 输入级采用互补结构进一步降低了功耗; 为了消除传统结构所引入的高阻节点,提出了低输出阻抗的AB类驱动电路,提高了带宽。仿真结果表明,在负载为20 pF的片内滤波电容的情况下,参考电压缓冲器的功耗为27 mW,建立时间小于2.5 ns,与相近性能的电路相比,所提电路的功耗更低。其中运放的单位增益带宽为602 MHz,相位裕度为61°。所提出的参考电压缓冲器应用于一款双通道14位200 MHz的流水线ADC中,测试结果表明,ADC的信号噪声失真比达到73 dB,所提出的电路结构能以较低的功耗实现较高的精度和速度。
Abstract:
For solving the problem that the internal reference voltage buffer of high-speed analog-to-digital converter(ADC)has to consume large power to achieve high accuracy and high sampling rate, a fully differential reference voltage buffer with an asymmetric class-AB output stage is presented. The voltage buffer achieves high precision with a relatively low op-amp gain, which significantly reduces the power consumption of the buffer. By introducing an asymmetric output structure, the circuit only needs to satisfy large bandwidth but no longer needs a high open-loop gain, and the input stage uses a complementary structure to further reduce power consumption. A class-AB driving circuit with low output impedance eliminates the high-resistance nodes introduced by the common structure and increases the bandwidth. Simulation results show that the power consumption of this reference voltage buffer is 27 mW and the settling time is less than 2.5 ns when driving a 20 pF on-chip filtering capacitor, implying an obvious drop in power consumption compared with other circuits with similar performance. The operational amplifier in the buffer has an unity-gain bandwidth of 602 MHz and a phase margin of 61 degrees. The proposed reference voltage buffer is used in a two-channel, 200 MHz, 14 b pipelined ADC. The test results of the ADC chip show that the signal-to-noise and distortion ratio(SNDR)of the ADC is 73 dB, which suggests that the proposed circuit can achieve higher accuracy and speed with higher power efficiency.

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备注/Memo

备注/Memo:
收稿日期: 2019-09-23。作者简介: 焦子豪(1996—),男,硕士生; 张鸿(通信作者),男,教授,博士生导师。基金项目: 国家自然科学基金资助项目(61974118)。
更新日期/Last Update: 2020-05-10