[1]黄绪,梁煜,张为,等.高性能的图像无损压缩知识产权核设计[J].西安交通大学学报,2020,54(05):102-108+123.[doi:10.7652/xjtuxb202005014]
 HUANG Xu,LIANG Yu,ZHANG Wei,et al.Design of Intellectual Property Core for High-Performance Image Lossless Compression[J].Journal of Xi'an Jiaotong University,2020,54(05):102-108+123.[doi:10.7652/xjtuxb202005014]
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高性能的图像无损压缩知识产权核设计
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《西安交通大学学报》[ISSN:0253-987X/CN:61-1069/T]

卷:
54
期数:
2020年第05期
页码:
102-108+123
栏目:
出版日期:
2020-05-10

文章信息/Info

Title:
Design of Intellectual Property Core for High-Performance Image Lossless Compression
文章编号:
0253-987X(2020)05-0102-07
作者:
黄绪 梁煜 张为 郝亚喆
天津大学微电子学院, 300072, 天津
Author(s):
HUANG Xu LIANG Yu ZHANG Wei HAO Yazhe
School of Microelectronics, Tianjin University, Tianjin 300072, China
关键词:
图像无损压缩 知识产权核 超大规模集成电路 离散小波变换
Keywords:
image lossless compression intellectual property core VLSI circuit discrete
分类号:
510.1035
DOI:
10.7652/xjtuxb202005014
文献标志码:
A
摘要:
为了解决海量图像数据对存储介质和有限的带宽造成的巨大压力,提出了高性能的图像无损压缩知识产权(IP)核,给出了相应的超大规模集成电路(VLSI)架构。通过对图像预处理模块进行兼容性优化,使其可以灵活处理多种规格的图像; 优化离散小波变换(DWT)模块,提出了单加法器延时结构,使离散小波变换模块的最高工作频率达274 MHz; IP核整体架构采用串并复用流水线设计思路,图像预处理和离散小波变换模块串行处理数据,算术编码和位平面编码模块并行处理数据,IP核内的所有模块均采用流水线设计方法,最终大幅提升IP核的吞吐率。实验结果表明,设计的IP核可直接接收光电耦合器件(CCD)相机的图像数据完成无损压缩并输出码流,该IP核在Xilinx Kintex-7 KC705开发板上实现,最高工作频率达171 MHz,最大吞吐率达1 472 Mb/s,与现有图像无损压缩VLSI编码器相比,最高工作频率提升16%以上,最大吞吐率提升25%以上。
Abstract:
To reduce the heavy burden by the massive image data on the storage medium and limited bandwidth, an intellectual property(IP)core is proposed for high-performance image lossless compression, and the corresponding VLSI circuit structure is given. The image pre-processing structure is optimized for compatibility, so that it can flexibly process images of multiple specifications. The discrete wavelet transform structure is optimized, and a single adder delay structure is proposed, so that the maximum working frequency of the discrete wavelet transform module is 274 MHz. The serial-parallel multiplexing pipeline design is proposed for the overall structure, and discrete wavelet transform module is used as a multiplexing module. The arithmetic coding and bit plane coding modules are used together as parallel modules, so the throughput of IP core is greatly improved. The experimental results show that the IP core of this design can directly receive the image data of the CCD camera to perform lossless compression and output the code stream. The maximum operating clock of this IP core on the Xilinx Kintex-7 KC705 development board is 171 MHz, with a maximum throughput of 1 472 Mb/s. Compared with the existing image lossless compression VLSI structure, the maximum operating frequency is increased by more than 16%, and the maximum throughput is increased by more than 25%.

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备注/Memo

备注/Memo:
收稿日期: 2019-11-30。作者简介: 黄绪(1995—),男,硕士生; 张为(通信作者),男,教授,博士生导师。基金项目: 光电信息控制和安全技术重点实验室资助项目(JCKY2019210C053); 国家重点研发计划资助项目(2016YFE0100400)。
更新日期/Last Update: 2020-05-10